|
x86 architecture
CPUID
Before trying to rely upon CPUID, a program must properly detect and sometimes enable the instruction. In particular, it must
detect the presence of a 32-bit x86 processor, which supports the EFLAGS register. Next, for a Cyrix or a NexGen processor,
the CPUID instruction may have to be enabled. Then the program must try to toggle the ID bit in the EFLAGS register, to see
whether the instruction is supported or not. Note that the program could face one of the early Intel P5 processors that did not
return a vendor ID string or maximum supported standard leaf when leaf 0000_0000h was queried. Last but not least, various
processors do support a partially programmable CPUID instruction... thanks to developers who hard-coded "GenuineIntel" all
over the place. And then there are of course hypervisors and hardware or software emulators... which can report whatever...
|
|
|
CPUID at CPL>0 outside SMM may #GP on Intel processors.
This is supported if MSR CEh[31]=1, and controlled by MSR 140h[0]=1.
|
CPUID is serializing, but SERIALIZE should be used instead.
Typically leaf 0000_0000h has the lowest latency. Also, fundamentally latency may be variable.
|
|
|
CPUID at CPL>0 outside SMM may #GP on AMD processors.
This is supported if CPUID 8000_0021h.EAX[17]=1, and controlled by MSR C001_0015h[35]=1.
|
CPUID primarily operates on registers EAX-EBX-ECX-EDX.
On Intel processors with microcode update support and MSRs, CPUID writes MSR 0000_008Bh.
|
0000_
standard leaves
Intel-defined
|
0000h
max + ID
|
0001h
FMS🌹flags
P4 P6 more Kn Zn |
0002h
caches
v1 – old |
0003h
PSN
|
0004h
caches
v2 – new |
0005h
MON
|
0006h
pwr mgmt
|
0007h
flags
|
0008h
reserved
|
0009h
DCA
|
000Ah
perf mon
|
000Bh
topology
v1 – old |
000Ch
reserved
|
000Dh
X state
|
000Eh
reserved
|
000Fh
RDT-M
QoS monitoring |
0010h
RDT-A
QoS allocation |
0011h
reserved
|
0012h
SGX
|
0013h
reserved
|
0014h
PT
|
0015h
frequency
clock – TSC |
0016h
frequency
base – max – bus |
0017h
attributes
ID – brand |
0018h
TLB
|
0019h
KL
|
001Ah
core model
|
001Bh
PCONFIG
|
001Ch
LBR
|
001Dh
AMX
tile |
001Eh
AMX
TMUL |
001Fh
topology
v2 – new |
0020h
HRESET
|
0021h
TDX
|
0022h
reserved
|
0023h
perf mon
extended |
0024h
AVX10
|
0025h
reserved
|
0026h
reserved
|
0027h
asy RDT-M
QoS monitoring |
0028h
asy RDT-A
QoS allocation |
0029h
APX
|
002Ah
reserved
|
002Bh
reserved
|
002Ch
reserved
|
002Dh
reserved
|
002Eh
reserved
|
002Fh
reserved
|
0030h
reserved
|
0031h
reserved
|
0032h
reserved
|
0033h
reserved
|
0034h
reserved
|
0035h
reserved
|
0036h
reserved
|
0037h
reserved
|
|
2000_
optional leaves
e.g. Xeon Phi
|
0000h
max
|
0001h
flags
|
0002h
reserved
|
0003h
reserved
|
0004h
reserved
|
0005h
reserved
|
0006h
reserved
|
0007h
reserved
|
|
4000_
hypervisor leaves
e.g. Microsoft
|
0000h
vendor
|
0001h
interface
|
0002h
version
|
0003h
features
|
0004h
recomm.
|
0005h
limits
|
0006h
hardware
|
0007h
CPU mgmt
|
0008h
SVM feat
|
0009h
nested feat
|
000Ah
nested virt
|
undocumented
000Bh
unknown
|
000Ch
isolation cfg
|
000Dh
reserved
|
000Eh
reserved
|
000Fh
reserved
|
deprecated
0080h
SYNDBG
vendor + max |
deprecated
0081h
SYNDBG
interface |
deprecated
0082h
SYNDBG
platform cap's |
0083h
reserved
|
0084h
reserved
|
0085h
reserved
|
0086h
reserved
|
0087h
reserved
|
uncodumented
0080h
unknown
unknown |
undocumented
0081h
virtual stack
interface |
undocumented
0082h
virtual stack
properties |
0083h
reserved
|
0084h
reserved
|
0085h
reserved
|
0086h
reserved
|
0087h
reserved
|
|
4C78_
supervisor leaves
e.g. Linux ("Lx")
|
0000h
reserved
|
0001h
flags
|
0002h
bugs
|
0003h
reserved
|
0004h
reserved
|
0005h
reserved
|
0006h
reserved
|
0007h
reserved
|
|
8000_
extended leaves
AMD-defined
|
0000h
max + ID
|
0001h
FMS + flags
|
0002h -- 0003h -- 0004h
processor name string
|
0005h
L1
caches & TLBs |
0006h
L2/L3
caches & TLBs |
0007h
capabilities
|
0008h
addr + misc
|
0009h
reserved
|
000Ah
SVM
|
000Bh
reserved
|
000Ch
reserved
|
000Dh
reserved
|
000Eh
reserved
|
000Fh
reserved
|
0010h
reserved
|
0011h
reserved
|
0012h
reserved
|
0013h
reserved
|
0014h
reserved
|
0015h
reserved
|
0016h
reserved
|
0017h
reserved
|
0018h
reserved
|
0019h
1G TLB
|
001Ah
perf hints
|
001Bh
IBS
|
001Ch
LWP
|
001Dh
caches
|
001Eh
topology
v1 – old |
001Fh
SME/SEV
|
0020h
PQoS
|
0021h
features
|
0022h
perf mon
|
0023h
HMK
|
0024h
reserved
|
0025h
RMP
|
0026h
topology
v2 – new |
0027h
WL class
|
0028h
reserved
|
0029h
reserved
|
002Ah
reserved
|
002Bh
reserved
|
002Ch
reserved
|
002Dh
reserved
|
002Eh
reserved
|
002Fh
reserved
|
|
8086_
vendor leaves
Transmeta
|
0000h
max + ID
|
0001h
FMS + flags
|
0002h
HW/SW rev
|
0003h -- 0004h -- 0005h -- 0006h
CMS info string
|
0007h
MHz + mV
|
|
8C86_
vendor leaves
Hygon
|
0000h
max + flags
|
0001h
reserved
|
0002h
reserved
|
0003h
reserved
|
0004h
reserved
|
0005h
reserved
|
0006h
reserved
|
0007h
reserved
|
|
C000_
vendor leaves
Centaur & Zhaoxin
|
0000h
max + ID
|
0001h
FMS + flags
|
0002h
unknown
|
0003h
unknown
|
0004h
unknown
|
0005h
isolation
|
0006h
flags
|
0007h
reserved
|
|
E000_
vendor leaves
to be disclosed
|
As of 2025 this range
is in active use by a
corporate entity other
than Intel or AMD. |
|
8FFF_
prank leaves
AMD
|
FFF8h
reserved
|
FFF9h
reserved
|
FFFAh
reserved
|
FFFBh
reserved
|
FFFCh
reserved
|
FFFDh
reserved
|
FFFEh
DEI
|
FFFFh
prank
|
|
0000_
prank leaves
Rise mP6
|
5A48h
reserved
|
5A49h
reserved
|
5A4Ah
reserved
|
5A4Bh
reserved
|
5A4Ch
reserved
|
5A4Dh
reserved
|
5A4Eh
prank
|
5A4Fh
reserved
|
|
xxxx_
reserved leaves
any vendor
|
xxxxh
reserved
|
xxxxh
reserved
|
xxxxh
reserved
|
xxxxh
reserved
|
xxxxh
reserved
|
xxxxh
reserved
|
xxxxh
reserved
|
xxxxh
reserved
|
standard leaf 0000_0000h
|
|
| input |
EAX=0000_0000h |
get maximum supported standard leaf and vendor ID string |
|
| output |
EAX=xxxx_xxxxh |
maximum supported standard leaf #1 |
| EBX-EDX-ECX |
vendor ID string #2 |
| GenuineIntel |
Intel |
| UMC UMC UMC |
UMC |
| AuthenticAMD |
AMD |
| CyrixInstead |
Cyrix (Aug 1999: VIA buys Cyrix from NatSemi for $167M) (Jul 1997: NatSemi buys Cyrix for $550M) |
| NexGenDriven |
NexGen (Jan 1996: AMD buys NexGen for $800M) |
| CentaurHauls |
Centaur (IDT) (Sep 1999: VIA buys Centaur from IDT for $51M) |
| RiseRiseRise |
Rise Technology (Oct 1999: SiS buys Rise for $?M) |
| SiS SiS SiS |
SiS (ex-Rise) |
| GenuineTMx86 |
Transmeta (Jan 2009: Novafora buys Transmeta for $255M) |
| Geode by NSC |
National Semiconductor (Aug 2003: AMD buys Geode) |
| Vortex86 SoC |
DM&P (ex-SiS) |
| Genuine RDC |
RDC (ex-SiS) |
| HygonGenuine |
Hygon – AMD lineage (Zen1 & Zen2) (Apr 2016 for $293M) – (Jun 2019: US DoC BIS EAR entity list) |
| Shanghai |
Zhaoxin – Centaur lineage (Isaiah) (Oct 2020 for $138M) – (Nov 2021: Intel buys team for $125M) |
|
| GenuineIntel |
Jintide – Intel CPU + ITR + RCP
custom – ITR is an I/O trace chip – RCP is a reconfigurable control processor
as of 2026, Montage sells the products, covering the SKX to GNR/SRF range |
| GenuineIotel |
Intel
single HSW Xeon E3-1231 v3 chip with a 1-bit error (6E > 6F), reported here |
|
| notes |
descriptions |
|
| #1 |
According to [1] and [2] the pre-B0 step Intel P5 processors return EAX=0000_05xxh. |
| #2 |
According to [1] and [2] the pre-B0 step Intel P5 processors don't return a vendor ID string. |
| |
For more "archeology" covering #1 and #2, see Konstantin Belousov's site here, and Geoff Chappell's site here. |
standard leaf 0000_0001h
|
|
| input |
EAX=0000_0001h |
get processor type/family/model/stepping and feature flags |
|
| output |
EAX=xxxx_xxxxh |
processor type/family/model/stepping |
| reserved |
Currently unused. Future processors may use bits 31...28. |
extended family
(added to family)
|
The extended processor family is encoded in bits 27...20. |
|
00+F |
Intel P4
Transmeta Efficeon
AMD K8 (Fam 8)
|
| 01+F |
AMD K9 (Fam 9) (cancelled)
AMD K8L (Fam 10h)
|
| Intel Itanium 2 (IA-64) |
| 02+0 |
Intel Itanium 2 DC (IA-64)
Intel Itanium 2 QC (IA-64)
|
| 02+1 |
Intel Itanium 2 8C (IA-64) |
| 02+F |
AMD K8 (Fam 11h) |
| 03+F |
AMD K8L (Fam 12h) |
| Intel (Fam 12h = 18) |
| 04+F |
Intel (Fam 13h = 19) |
| 05+F |
AMD BC (Fam 14h) |
| 06+F |
AMD BD (Fam 15h) – BD PD SR XV |
| 07+F |
AMD JG (Fam 16h) |
| 08+F |
AMD ZN (Fam 17h) – Zen1 and Zen2 |
| 09+F |
AMD ZN (Fam 18h) – Hygon |
| 0A+F |
AMD ZN (Fam 19h) – Zen3 and Zen4 |
| 0B+F |
AMD ZN (Fam 1Ah) – Zen5 and Zen6 |
extended model
(concatenated with model)
|
The extended processor model is encoded in bits 19...16. |
|
0...F |
see 2-digit models below |
| reserved |
Currently unused. Future processors may use bits 15...14. |
| type |
The processor type is encoded in bit 13 and bit 12. |
|
11b |
reserved |
| 10b |
secondary processor (for MP) (not on 486) |
| 01b |
Overdrive processor |
| 00b |
primary processor |
| family |
The family is encoded in bits 11...8. |
|
4 |
most 80486s
AMD 5x86
Cyrix 5x86
|
| 5 |
Intel P5, P54C, P55C, P24T
Intel Quark
Intel SCC (very likely but unconfirmed)
NexGen Nx586
Cyrix M1
Cyrix MediaGX
Geode
AMD K5, K6
Centaur C6, C2, C3
Rise mP6, mP6-II
SiS 55x
DM&P Vortex DX/MX
RDC IAD
Transmeta Crusoe
|
| 6 |
Intel P6, P2, P3, PM, Core 2
Intel Atom
Intel Xeon Phi (KNL and KNM)
AMD K7
Cyrix M2
VIA C3
Zhaoxin CN
DM&P Vortex DX3
|
| 7 |
Zhaoxin ZX
Intel Itanium (IA-64)
|
| B |
Intel Xeon Phi (KNF and KNC)
|
| F |
refer to extended family
|
| 0 |
refer to extended family
|
| model |
The model is encoded in bits 7...4. |
| ancient processors |
| Intel 80486 |
0 |
i80486DX-25/33 |
| 1 |
i80486DX-50 (FMS=415h has CPUID X87 VME) |
| 2 |
i80486SX |
| 3 |
i80486DX2 (FMS=435h has CPUID X87 VME) |
| 4 |
i80486SL |
| 5 |
i80486SX2 |
| 7 |
i80486DX2WB |
| 8 |
i80486DX4 (FMS=480h has CPUID X87 VME) |
| 9 |
i80486DX4WB (FMS=490h has CPUID X87 VME PSE) |
| UMC 80486 |
1 |
U5D |
| 2 |
U5S |
| AMD 80486 |
3 |
80486DX2 |
| 7 |
80486DX2WB |
| 8 |
80486DX4 |
| 9 |
80486DX4WB |
| A |
Elan SC400 |
| E |
5x86 |
| F |
5x86WB |
| Cyrix 5x86 |
9 |
5x86 |
| Cyrix MediaGX |
4 |
GX, GXm |
| Intel P5-core |
0 |
P5 A-step |
| 1 |
P5 |
| 2 |
P54C |
| 3 |
P24T Overdrive |
| 4 |
P55C |
| 7 |
P54C |
| 8 |
P55C (0.25µm) |
| Intel Quark |
9
Lakemont
(not LMT) |
X1000 400 MHz 16 KiB x86 P5 with x87 NX (Clanton=CLN)
C1000 32 MHz 8 KiB x86 P5 without x87 NX (Atlas Peak)
D2000 32 MHz 0 KiB x86 P5 without x87 NX (Mint Valley)
D1000 32 MHz 0 KiB x86 sub-set w/o x87 NX (Silver Butte)
note: the D1000 has no CPUID, and no EDX=FMS after RESET
|
| A |
unknown and unconfirmed |
| NexGen Nx586 |
0 |
Nx586 or Nx586FPU (only later ones) |
| Cyrix M1 |
2 |
6x86 |
| Cyrix M2 |
0 |
6x86MX |
| Geode |
4 |
GX1, GXLV, GXm |
| 5 |
GX2 |
| A |
LX |
| AMD K5 |
0 |
SSA5 (PR75, PR90, PR100) |
| 1 |
5k86 (PR120, PR133) |
| 2 |
5k86 (PR166) |
| 3 |
5k86 (PR200) |
| AMD K6 |
6 |
K6 (0.30 µm) |
| 7 |
K6 (0.25 µm) |
| 8 |
K6-2 |
| 9 |
K6-III |
| C |
K6-2+ (source) (0.18 µm) |
| D |
K6-2+ or K6-III+ (0.18 µm) |
| Centaur |
4 |
C6 |
| 8 |
C2 |
| 9 |
C3 |
| VIA C3 |
5 |
Cyrix M2 (Joshua) (Cayenne core, aka Gobi) |
| 6 |
WinChip C5A (Samuel) |
| 7 |
WinChip C5B (if stepping = 0...7) (Samuel-2) (+L2) |
| 7 |
WinChip C5C (if stepping = 8...F) (Ezra) |
| – |
WinChip C5M (unreleased – C5N pathfinder Ezra-T) |
| 8 |
WinChip C5N (if stepping = 0...7) (Ezra-T) (+T-bus) |
| 8 |
WinChip C5X (if stepping = 8...F) (Nehemiah) (SSE) |
| 9 |
WinChip C5XL (if stepping = 0...7) (Nehemiah shrink) |
| – |
WinChip C5XP (unreleased – C5XL w/ low power) |
| – |
WinChip C5Y (unreleased – high speed & SSE2) |
| – |
WinChip C5Z (unreleased – VIA V4 system bus) |
| 9 |
WinChip C5P (if stepping = 8...F) (Nehemiah-P) (DP) |
| – |
WinChip C5Q (unreleased – 130nm TSMC Esther) |
| – |
WinChip C5R (unreleased – 110nm TSMC Esther) |
| – |
WinChip C5IBM (unfinished – C5J pathfinder Esther) |
| A |
WinChip C5J model A (IBM) (Esther) (+SHA) |
| D |
WinChip C5J model D (Fujitsu) (Esther) (+SHA) |
| – |
WinChip C5W (unrealized variant: 90nm IBM SOIv2) |
| VIA CN |
F |
WinChip CNA (x64) (if stepping < 8) (Isaiah) |
| F |
WinChip CNB A1 (if stepping = 8) |
| F |
WinChip CNB A2 (if stepping = A) |
| F |
WinChip CNC A1 (if stepping = C) (if 1x 2c)
WinChip CNQ A1 (if stepping = C) (if 2x 2c)
|
| F |
WinChip CNC A2 (if stepping = D) (if 1x 2c)
WinChip CNQ A2 (if stepping = D) (if 2x 2c) ZX-A
|
| F |
WinChip CNR (4c) (if stepping = E) (AVX2) ZX-B |
| 47 |
WinChip CNS (8c) (CHA SoC 16M) (AVX512) final |
Zhaoxin CN
CNQ/CNR -> ZX-C -> KX/KH
transition period |
0F |
ZX-C Zhangjiang (KaiXian/KaisHeng) |
| 19 |
ZX-C Zhangjiang (KaiXian/KaisHeng) |
| 1F |
ZX-D Zhangjiang (KaiXian/KaisHeng) |
| |
ZX-C and ZX-C+ fail to properly restore CR4.FSGSBASE=1
during RSM. This causes subsequent FSGSBASE accesses
to #UD. These microcode updates should address the issue:
000006fe_00000001_20180726_6e07329b (0x20A)
000006fe_00000001_20180726_6e1e984b (0x210)
00010690_00000001_20180726_0c55f25d (0x20?)
00010690_00000001_20180726_41faefde (0x210)
To check at runtime:
If ((MSR 0x1232 >> 15) & 0x7) == 0), ucode ≥0x20E is fixed.
If ((MSR 0x1232 >> 15) & 0x7) == 1), ucode ≥0x208 is fixed.
|
| Zhaoxin ZX |
0B |
ZX-C (28nm) Zhangjiang ZX-C KH-10 & ZX-C+ |
| 1B |
ZX-D (28nm) Wudakou KX-5 KH-20 |
| 3B |
ZX-E (16nm) Lujiazui KX-6 KH-30 |
| 4X |
ZX-F (16nm) see CNS |
| 5B |
ZX-G (16nm) Yongfeng –––– KH-40 (~CNS–) |
| 6B |
ZX-H (??nm) Shijidadao KX-7 KH-50 |
| Rise |
0 |
mP6 (0.25 µm) |
| 2 |
mP6 (0.18 µm) |
| 8 |
mP6-II (0.25 µm) |
| 9 |
mP6-II (0.18 µm) |
| SiS |
0 |
55x |
| DM&P |
2 |
Vortex DX |
| 8 |
Vortex MX |
| DM&P |
1 |
Vortex DX3 (2c) |
| RDC |
8 |
RDC IAD 100 |
| Transmeta Crusoe |
4 |
TM3x00 and TM5x00 (Wilma and Fred) |
| Transmeta Efficeon |
2 |
TM8000 (130 nm) (Astro) |
| 2 |
TM8000 (90 nm CMS 6.0) |
| 3 |
TM8000 (90 nm CMS 6.1+) |
| exotic extinct Intel processors |
Intel P4-core
-------------------------
WMT NWD PSC TEJ CDM
FOS GAL POT JHK TUL
Willamette | Foster
Northwood | Gallatin
Prescott | Potomac
Tejas | Jayhawk
Cedar Mill | Tulsa
-------------------------
|
0 |
P4 (180 nm) (WMT) |
| 1 |
P4 (180 nm) (WMT and FOS) |
| 2 |
P4 (130 nm) (NWD and GAL) |
| 3 |
P4 (90 nm) (PSC) |
| 4 |
P4 (90 nm) (PSC and POT) |
| 5 |
P4 (90 nm) (TEJ and JHK) (cancelled) |
| 6 |
P4 (65 nm) (CDM and TUL) |
| classic Intel processors |
Intel P6-core
(in historic order)
-------------------------
this "decoder ring" for
three letter acronyms
only covers those Intel
cores and chips which
are in use on this page
------ large cores ------
CPC Cypress Cove SNC14
PMC Palm Cove 10
SNC Sunny Cove 10+
WLC Willow Cove 10++
OLC Olive Cove 10++-
GLC Golden Cove 10+++
RPC Raptor Cove 10++++
7 --> i4 | 5 --> i20A
7+ --> i3 | 5+ --> i18A
RWC Redwood Cove i4
RWC+ Redwood Cove+ i3
LNC Lion Cove N3B
CGC Cougar Cove i18A
CYC Coyote Cove i18A+
PNC Panther Cove i18A+
------ small cores ------
BNL Bonnell
SLT Saltwell
SLM Silvermont
AMT Airmont
GLM Goldmont
GLP Goldmont Plus
DMT Delmont (skip)
TNT Tremont
GRM Gracemont
GRP Gracemont Plus
CRM Crestmont i4
CRM+ Crestmont+ i3
SKM Skymont
DKM Darkmont
SGL Sierra Glen
OGL Oak Glen
FGL Fern Glen
ARW Arrow Wolf
----- Atom CPU line -----
DMV Diamondville
PNV Pineview
SVT Silverthorne
LCR Lincroft
CDV Cedarview
PWL Penwell
CLV Cloverview
TGR Tangier
ANN Anniedale
BYT Bay Trail
VLV Valleyview
CMT Cougar Mountain
LMT Lightning Mountain
BSW Braswell
APL Apollo Lake
GLK Gemini Lake
JSL Jasper Lake
EHL Elkhart Lake
TWL Twin Lake -> ADL-N
ASL Amston Lake -> ADL-N
MDF Medfield -> PWL
MRF Merrifield -> TGR
MOF Moorefield -> ANN
CHT Cherry Trail-> BSW
LKF Lakefield SNC+TNT
----- Core CPU line -----
MRM Merom
PNR Penryn
NHM Nehalem
WSM Westmere
HSW Haswell
BDW Broadwell
SNB Sandybridge
IVB Ivybridge
SKL Sky Lake
KBL Kaby Lake
CFL Coffee Lake
WHL Whiskey Lake
AML Amber Lake
CML Comet Lake
RKL Rocket Lake
CNL Cannon Lake
ICL Ice Lake
TGL Tiger Lake
ADL Alder Lake
RPL Raptor Lake
BTL Bartlett Lake
MTL Meteor Lake
LNL Lunar Lake
ARL Arrow Lake
WCL Wildcat Lake
PTL Panther Lake
NVL Nova Lake
JSF Jasper Forest
CFD Cloverfield
LFD Lynnfield
ABD Auburndale
HVD Havendale
ARD Arrandale
CLD Clarkdale
----- Xeon CPU line -----
CTN Clovertown EP
HTN Harpertown
GTN Gainestown
GFT Gulftown
JKT Jaketown
IVT Ivytown
TIG Tigerton EX
DUN Dunnington
BEC Beckton
EGT Eagleton
NHX Nehalem EP/EX
WSX Westmere
HSX Haswell
BDX Broadwell
SNX Sandybridge (skip)
IVX Ivybridge
SKX Sky Lake
CLX Cascade Lake +AEP
CPX Cooper Lake +BF16
CNX Cannon Lake (skip)
ICX Ice Lake
BDE Broadwell D DE
HWL Hewitt Lake
SPR Sapphire Rapids P
EMR Emerald Rapids
GNR Granite Rapids
DMR Diamond Rapids
SRF Sierra Forest E
CWF Clearwater Forest
RRF Rogue River Forest
AVN Avoton NS
DVN Denverton
SNR Snow Ridge
GRR Grand Ridge
RLY Rangeley -> AVN
JVL Jacobsville -> SNR
-------------------------
|
0 |
P6 A-step |
| 1 |
P6 |
| 3 |
P2 (0.28 µm) external L2 (Klamath) |
| 5 |
P2 (0.25 µm) external L2 (Deschutes) (Tonga) |
| 6 |
P2 (0.25 µm) 256 KB L2 (Dixon) |
| 7 |
P3 (0.25 µm) external L2 (Katmai) (Tanner) |
| 8 |
P3 (0.18 µm) 256 KB L2 (Coppermine) |
| A |
P3 (0.18 µm) 2 MB L2 (Cascades) |
| B |
P3 (0.13 µm) 512 KB L2 (Tualatin) |
| C |
P3 (0.18 µm) with 128 KB on-die L2 GFX (Timna)
note: one working system did report 692h (aka Banias) instead?! |
| 9 |
PM (0.13 µm) with 1 MB on-die L2 (Banias) (695h) |
| D |
PM (0.09 µm) with 2 MB on-die L2 (Dothan) |
| E |
PM DC (65 nm) with 2 MB on-die L2 (Yonah) |
| 15 |
EP80579 (65 nm) with 256 KB on-die L2 (Tolapai) |
| F |
Core 2 2C (65 nm) 4 MB L2 (MRM – Merom) |
| 16 |
Core 2 1C (65 nm) 1 MB L2 (MRM – Merom-L) |
| 17 |
Core 2 2C (45 nm) 6 MB L2 (PNR – Penryn) |
| 1D |
Core 2 6C (45 nm) 3x3 MB L2 + 16 MB L3 (DUN) |
| 1A |
Core 7 4C (45 nm) 8 MB L3 QPI (NHM) |
| 1E |
Core 7 4C (45 nm) 8 MB L3 PCIe (CFD/LFD/JSF) |
| 1F |
Core 7 2C (45 nm) 4 MB L3 GFX (ABD/HVD) |
| 2E |
Core 7 8C (45 nm) 24 MB L3 QPI (BEC) |
| 2C |
Core 7 6C (32 nm) 12 MB L3 QPI (WSM) |
| 25 |
Core 7 2C (32 nm) 4 MB L3 GFX (ARD/CLD) |
| 2F |
Core 7 10C (32 nm) 30 MB L3 QPI (WSM-EX) |
| 2A |
Core 7 4C (32 nm) 8 MB L3 GPU (SNB-DT) |
| 2D |
Core 7 8C (32 nm) 20 MB L3 PCIe (SNB-E[NPX]) |
| 3A |
Core 7 4C (22 nm) 8 MB L3 GPU (IVB-DT) |
| 3E |
Core 7 15C (22 nm) 37.5 MB L3 PCIe (IVB-E[NPX]) |
| 3C |
Core 7 4C (22 nm) 8 MB L3 GPU (HSW-DT) |
| 3F |
Core 7 18C (22 nm) 45 MB L3 PCIe (HSW-E[NPX]) |
| 45 |
HSW low power |
| 46 |
HSW Crystalwell (4C 6M GPU + 128M eDRAM) |
| 3D |
Core 7 2C (14 nm) 4 MB L3 GPU (BDW-DT) |
| 4F |
Core 7 24C (14 nm) 60 MB L3 PCIe (BDW-E[NPX]) |
| 56 |
Core 7 8C (14 nm) 12 MB L3 SoC (BDW-DE,HWL) |
| 47 |
BDW Brystalwell (4C 6M GPU + 128M eDRAM) |
| 4E |
SKL Y/U |
| 5E |
SKL S/H |
| 8E |
KBL Y/U and CFL Y/U and WHL U and AML Y |
| 9E |
KBL S/H and CFL S/H and WHL S/H |
| A6 |
CML Y/U |
| A5 |
CML S/H |
| A8! |
RKL Y/U (14 nm SNC aka CPC) (not productized) |
| A7 |
RKL S/H (14 nm SNC aka CPC) |
| 55 |
SKX (S=0/1/2/3/4), CLX (S=5/6/7), CPX (S=A/B) |
| 66 |
CNL Y/U (10 nm PMC) |
| 67 |
CNL S/H (10 nm PMC) (not productized) |
| 7E |
ICL Y/U (10+ nm SNC) |
| 7D |
ICL S/H (10+ nm SNC) (not productized) |
| 9D |
ICL NNP-I (10+ nm SNC + Nervana Spring Hill) |
| 6A |
ICX (10+ nm SNC) |
| 6C |
ICX D (10+ nm SNC) |
| 8A |
LKF (10+ nm 1xSNC + 4xTNT) |
| 8C |
TGL Y/U (10++ nm WLC) |
| 8D |
TGL S/H (10++ nm WLC) |
| 9A |
ADL Y/U (10+++ nm 6xGLC + 8xGRM) |
| 97 |
ADL S/H (10+++ nm 8xGLC + 8xGRM) |
| BE |
ADL N (10+++ nm 0xGLC + 8xGRM) (aka TWL/ASL) |
| 8F |
SPR (10+++ nm GLC) |
| BA |
RPL U/P/H (10++++ nm i7 6xRPC + 8xGRP) |
| B7 |
RPL S/HX (10++++ nm i7 8xRPC + 16xGRP) |
| BF |
RPL S/HX (10++++ nm i7 8xRPC + 8xGRP) |
| D7 |
BTL emb. (10++++ nm i7 12xRPC) |
| CF |
EMR (10++++ nm i7 RPC) |
| AA |
MTL U (7 nm i4 2xRWC + 8xCRM + N6 2xCRM)
MTL H (7 nm i4 6xRWC + 8xCRM + N6 2xCRM) |
| AB! |
MTL N (7 nm i4 0xRWC + ?xCRM) (not productized)
note: envisioned ADL N successor |
| AC |
MTL S (7 nm i4 6xRWC + 8xCRM) (not productized)
MTL S (7 nm i4 6xRWC + 16xCRM) (never assigned) |
| AD |
GNR (7+ nm i3 RWC+) |
| AE |
GNR D (7+ nm i3 RWC+) |
| BD |
LNL (TSMC N3B 4xLNC + 4xSKM + N6 0xCRM + 2-ch LP5X) |
| B5 |
ARL U (7+ nm i3 2xRWC+ + 8xCRM+ + N6 2xCRM)
note: basically MTL U, but i3 not i4 |
| C5 |
ARL H (TSMC N3B 6xLNC + 8xSKM + N6 2xCRM)
note: basically MTL H, but N3B not i4 |
| C6 |
ARL S (TSMC N3B 6xLNC + 8xSKM [A0])
ARL S (TSMC N3B 8xLNC + 16xSKM [B0])
note: basically MTL S, but N3B not i4 |
| CA |
ARL R (TSMC N3B? LNC? SKM? 8+32+2?) |
| D5 |
WCL (i18A CGC DKM 2+0+4) |
| CC |
PTL (i18A CGC DKM 4+0+4 4+8+4) |
| |
| 🌹 Need more details? |
Click the triangle to show/hide details for models that Intel used in the P4/P6/Atom era.
----------------------------------------------------------------------------------------------
Intel started with 00-0F, and then consistently used 5-6-7,A,C-D-E-F | A5 CML-S/H SKL ---
for the 1x-Dx range, with one "excursion" to 8,9,B for the Ax range. | A6 CML-Y/U SKL ---
----------------------------------------------------------------------+ A7 RKL-S/H 14SNC=CPC
The models for SC9861-G and KNH/KNB and KNP and KNB/KCV are unknown. | *A8 RKL-Y/U 14SNC=CPC
----------------------+-----------------------+-----------------------+ *A9 --- --- ---
00 P6 A-step 600nm | 25 WSM-DT ARD/CLD 32 |T 65 XMM7272 TSMC SLM | AA MTL-U/H RWC CRM
01 P6 B+ 600nm/350nm | 26 BNL-M. SVT/LCR 45 | 66 CNL-Y/U PMC | *AB MTL-N --- CRM
02 -- ----- | 27 SLT-M. PWL/MDF 32 | 67 CNL-S/H skip! PMC | AC MTL-S 6+8 RWC CRM
03 P2 ext.L2 280nm | 2A SNB SNB 32 | 6A ICX SNC | -- MTL-S 6+N RWC CRM
04 -- ----- | 2C WSM-EP GFT 32 | 6C ICX-D SNC |T -- ARL-S 6+8 LNC SKM
05 P2 ext.L2 250nm | 2D SNB-EP JKT 32 | 6D --- --- | AD GNR RWC+___
06 P2 int.L2 180nm | 2E NHM-EX BEC 45 | 6E CMT WiFi AMT | AE GNR-D RWC+___
07 P3 ext.L2 250nm | 2F WSM-EX EGT 32 | 6F --- --- | AF SRF SGL=CRM+
----------------------+-----------------------+-----------------------+-----------------------
08 P3 256K 180nm | 35 SLT-TAB CLV 32 | 75 LMT SC9853-I AMT | B5 ARL-U RWC+CRM+CRM
09 Banias 1M 130nm | 36 SLT CDV 32 | 76 --- --- | B6 GRR --- CRM
0A P3 2M 180nm | 37 SLM BYT/VLV 22 | 77 --- --- | B7 RPL-S/HX RPC GRP
0B P3 512K 130nm | 3A IVB-DT 22 | 7A GLK GLP | BA RPL-U/P/H RPC GRP
0C Timna 128K 180nm | 3C HSW-DT 22 | 7C --- --- | BC --- --- ---
0D Dothan 1c 2M 90nm | 3D BDW-DT 14 | 7D ICL-S/H skip! SNC |T BD LNL LNC SKM
0E Yonah 2c 2M 65nm | 3E IVB-X IVT 22 | 7E ICL-Y/U SNC | BE ADL-N --- GRM
0F MRM CTN/TIG 65nm | 3F HSW-X HSX 22 | 7F --- --- | BF RPL-S/HX RPC GRP
----------------------+-----------------------+-----------------------+-----------------------
15 Tolapai 256K 65nm | 45 HSW-ULT 22 | 85 KNM Phi |T C5 ARL-H LNC SKM CRM
16 MRM-L 1M 65nm | 46 HSW-G Cry`well 22 | 86 SNR/JVL TNT |T C6 ARL-S LNC SKM ---
17 PNR HTN 45nm | 47 BDW-G Bry`well 14 | 87 --- --- | C7 --- --- --- ---
1A NHM-EP GTN 45nm | 4A TGR/MRF SLM-M. 22 | 8A LKF SNC TNT |T CA ARL-R ??? ??? ???
1C BNL DMV/PNV 45 | 4C BSW/CHT AMT 14 | 8C TGL-Y/U WLC --- | CC PTL CGC DKM DKM
1D DUN 45 | 4D AVN/RLY SLM-D 22 | 8D TGL-S/H WLC --- | CD --- --- --- ---
1E NHM-DT CFD/LFD/JSF| 4E SKL-Y/U 14 -> 8E [3]-Y/U SKL --- | CE --- --- --- ---
1F NHM-G ABD/HVD 45 | 4F BDX 14 | 8F SPR GLC --- | CF EMR RPC --- ---
----------------------+-----------------------+-----------------------+-----------------------
F0 P4 WMT 180nm | 55 SKX/CLX/CPX [1] | 95 --- --- --- | D5 WCL CGC --- DKM
F1 P4 WMT,FOS 180nm | 56 BDE/HWL [2] | 96 EHL --- TNT | D6 --- --- --- ---
F2 P4 NWD,GAL 130nm | 57 KNL Phi | 97 ADL-S/H GLC GRM | D7 BTL RPC --- ---
F3 P4 PSC 90nm | 5A ANN/MOF SLM | 9A ADL-Y/U GLC GRM | DA --- --- --- ---
F4 P4 PSC,POT 90nm | 5C APL GLM | 9C JSL --- TNT | DC --- --- --- ---
F5 -- TEJ,JHK ? ---- |T 5D SoFIA TSMC SLM | 9D ICL-NNP-I SNC --- | DD CWF FGL=DKM ---
F6 P4 CDM,TUL 65nm | 5E SKL-S/H SKL -> 9E [4]-S/H SKL --- | DE --- --- --- ---
F7 -- ---- | 5F DVN GLM | 9F --- --- --- | DF --- --- --- ---
----------------------+-----------------------+-----------------------+-----------------------
[1] SKX steppings 0/1/2/3/4 = A1/A2/B0/B1/H0 | [3] 8E covered KBL-Y/U, CFL-Y/U, WHL-Y, AML-U
CLX steppings 5/6/7 = A0/B0/B1 | [4] 9E covered KBL-S/H, CFL-S/H, WHL-S/H
CPX steppings A/B = A0/A1 +-----------------------------------------------
[2] BDE steppings 1/2/3/4/5 = U0/V1/V2/Y0/A1 | Tick Tock broke when 10nm CNL didn't yield...
----------------------------------------------------------------------------------------------
|
Click the triangle to show/hide details for "generations" of Intel's vector instructions.
----------------------------------------------------------------------------------------------
SSE1 1999-02-26 KNI Katmai New Instructions
SSE2 2000-11-20 WNI Willamette New Instructions
SSE3 2004-02-02 PNI Prescott New Instructions
SSSE3 ~2006 goal TNI Tejas New Instructions ; TEJ cancelled
2006-06-26 MNI Merom New Instructions ; TNI survived!
SSE4.1 2008-01-07 PNI Penryn New Instructions
SSE4.2 2008-11-11 NNI Nehalem New Instructions
2010-01-07 WNI Westmere New Instructions + AES PCL
----------------------------------------------------------------------------------------------
AVX1 2011-01-09 SNB GNI = Gesher New Instructions
2012-04-29 IVB INI = IVB-NI = F16C RDRAND + SMEP
AVX2 2013-07-04 HSW HNI = HSW-NI
2014-10-27 BDW BNI = BDW-NI = ADCX/ADOX RDSEED PREFETCHW + SMAP
2015-08-05 SKL + MPX SGX
AVX3 2016-06-20 KNL F CD ER PF
AVX4 2017-07-11 SKX VL BW DQ
2017-12-xx KNM QFMA (QVNNI) QVNNIW
~2018 goal KNH DFMA ; KNH cancelled
AVX5 2018-05-15 PMC @ CNL IFMA VBMI
AVX6 2019-04-02 CLX VNNI
AVX7 2019-09-xx SNC @ ICL VPOPCNTDQ VBMI2 BITALG + VPCLMUL VAES GFNI
AVX8 2020-06-18 CPX BF16
AVX8 2020-09-02 WLC @ TGL VP2INTERSECT
2021-04-06 ICX
AVX9 2021-11-04 GLC @ ADL FP16 (BITALG2)
2022-10-20 RPC @ RPL
2023-01-10 SPR
2023-12-14 EMR
2023-12-14 RWC @ MTL
2024-09-03 LNC @ LNL AVX_IFMA AVX_NE_CONVERT AVX_VNNI_INT8 AVX_VNNI_INT16
and SHA512 SM3 SM4_VEX
AVX10.1 2024-09-24 GNR
AVX10.2 20yy-mm-dd NVL + DMR + MOVRS PREFETCHRST2 SM4_EVEX + APX
----------------------------------------------------------------------------------------------
AMXv1 2023-01-10 SPR TILE INT8 BF16
AMXv2a 2024-09-24 GNR FP16
AMXv2b 2025-04-dd GNR-D COMPLEX
AMXv3 20yy-mm-dd DMR MOVRS AVX512 FP8 TF32 (TRANSPOSE)
----------------------------------------------------------------------------------------------
|
| contemporary Intel processors |
Intel Core
(Fam 12h) |
00 |
never used, for reasons of software compatibility |
| 01 |
NVL (i18A+? CYC ARW 16+32+4?) |
| 03 |
NVL-L (i18A+? CYC ARW 8+16+4?) |
Intel Xeon
(Fam 13h) |
00 |
never used, for reasons of software compatibility |
| 01 |
DMR (i18A+? PNC) |
| Intel Atom processors |
Intel Atom
(in historic order)
-------------------------
"decoder ring" for Atom
-------------------------
Tick Tock original flow
SLM -> AMT 22 -> 14
GLM -> DMT 14 -> 10
TNT -> xxx 10 -> 7
note: TNT per Intel SDE
-------------------------
Tick Tock Tock new flow
AMT -> GLM -> GLP 14
TNT -> GRM -> GRP 10
CRM -> SKM -> DKM 7
SGL -> OGL -> FGL 7
CRM+ i3
-------------------------
SoC parts with AMT core
CMT Cougar Mountain
LMT Lightning Mountain
not to be confused with
Crestmont CRM Atom core
Lakemont the Quark core
-------------------------
|
1C |
Atom (45 nm BNL) 512 KB L2 (DMV/PNV) |
| 26 |
Atom (45 nm BNL) 512 KB L2 (SVT/LCR) |
| 36 |
Atom (32 nm SLT) 512 KB L2 (CDV) |
| 27 |
Atom (32 nm SLT) 512 KB L2 (PWL) |
| 35 |
Atom (32 nm SLT) 512 KB L2 (CLV) |
| 4A |
Atom 2C (22 nm SLM) 1 MB L2 + PwrVR (TGR) |
| 5A |
Atom 4C (22 nm SLM) 2 MB L2 + PwrVR (ANN) |
| 37 |
Atom 4C (22 nm SLM) 2 MB L2 + Gen7 (BYT/VLV) |
| 5D |
Atom 4C (28 nm SLM) 1 MB L2 + Mali (SoFIA) |
| 65 |
Atom 4C (28 nm SLM) 1 MB L2 + Mali (XMM7272) |
| 6E |
Atom 2C (14 nm AMT) 1 MB L2 + WiFi (CMT) |
| 75 |
Atom 8C (14 nm AMT) + Mali (LMT / SC9853-I) |
| ?? |
Atom 8C (14 nm AMT) + P.VR (LMT / SC9861-G) |
| 4C |
Atom 4C (14 nm AMT) 2 MB L2 + Gen8 (BSW) |
| 5C |
Atom 4C (14 nm GLM) 2 MB L2 + Gen9 LP (APL) |
| 7A |
Atom 4C (14 nm GLP) 4 MB L2 + Gen9 LP (GLK) |
| 9C |
Atom 4C (10 nm TNT) 4 MB L3 + Gen11 LP (JSL) |
| 96 |
Atom 4C (10 nm TNT) 4 MB L3 + Gen11 (EHL) |
Intel Atom
(micro server) |
4D |
Atom 8C (22 nm SLM) 4 MB L2 (AVN) |
| 5F |
Atom 16C (14 nm GLM) 16 MB L2 (DVN) |
| 86 |
Atom 24C (10 nm TNT) 27+15 MB L2+L3 (SNR) |
| B6 |
Atom 24C (i4 CRM) 24+?? MB L2+L3 (GRR) |
Intel Atom
(dense server) |
AF |
Atom 144C (i3 CRM+/SGL) 144+108 MB (SRF)
Atom 288C (dual die chip in limited production)
|
| DD |
Atom 288C (i18A DKM/FGL) 288+576 MB (CWF)
with 4 cores/tile, 6 tiles/die, 4 die/row, 3 rows/chip
|
| ?? |
Atom ???C (i18A+? ARW) ???+??? MB (RRF) |
| experimental Intel processors |
| Intel SCC |
? |
48C (45 nm) 12 MB L2 (SCC) (P54C) |
Intel Xeon Phi
----------------------
KNF Knights Ferry
KNC Knights Corner
KNL Knights Landing
KNM Knights Mill
----------------------
KNH Knights Hill
KNB Knights Bridge
KNP Knights Peak
KCV Knights Cove
----------------------
|
? |
32C (45 nm) 8 MB L2 (KNF) (L1OM) |
| 1 |
62C (22 nm) 31 MB L2 (KNC) (K1OM) |
| 57 |
72C (14 nm) 36 MB L2 (KNL) (AVX512) |
| 85 |
72C (14 nm) 36 MB L2 (KNM) (QF./QV.) |
| ?? |
88C (10 nm) ?? MB L2 (KNH) (KNL+1) |
| ?? |
88C (10 nm) ?? MB L2 (KNB) (KNM+1) |
| ?? |
108C (7 nm) ?? MB L2 (KNP) (KNH+1) |
| ?? |
??? (10 nm) ??? (KNB) (instead of KNH) |
| ?? |
??? (7 nm) ??? (KCV) (instead of KNP) |
| exotic extinct Intel processors |
| Intel Itanium |
0 |
Merced (180 nm) |
| Intel Itanium 2 |
0 |
McKinley (180 nm) |
| 1 |
Madison or Deerfield (130 nm) |
| 2 |
Madison 9M (130 nm) |
| Intel Itanium 2 DC |
0 |
Montecito (90 nm, 9000 series) |
| 1 |
Montvale (90 nm, 9100 series) |
| Intel Itanium 2 QC |
2 |
Tukwila (65 nm, 9300 series) |
| Intel Itanium 2 8C |
0 |
Poulson (32 nm, 9500 series)
Kittson (32 nm, 9700 series)
|
| classic AMD processors |
AMD K7
(Fam 7) |
0 |
Athlon (0.25 µm) (Argon) (Rev A/B) (bringup only) |
| 1 |
Athlon (0.25 µm) (Argon) (Rev C) (got productized) |
| 2 |
Athlon (0.18 µm) (Pluto/Orion) |
| 3 |
Duron (SF core) (Spitfire) |
| 4 |
Athlon (TB core) (Thunderbird) |
| 5 |
did not get productized (was MT Mustang) |
| 6 |
Athlon (PM core) (Palomino) (was CV Corvette) |
| 7 |
Duron (MG core) (Morgan) (was CM Camaro) |
| 8 |
Athlon (TH/AP core) (Thoroughbred/Appaloosa) |
| A |
Athlon (BT/TT core) (Barton/Thorton) |
AMD K8
(Fam 8)
(Hammer) |
0_xxxxb |
130 nm Rev C |
| 1_xxxxb |
90 nm Rev D |
| 2_xxxxb |
90 nm Rev E |
| 4_xxxxb |
90 nm Rev F |
| 5_xxxxb |
90 nm Rev F |
| 6_xxxxb |
65 nm Rev G |
| 7_xxxxb |
65 nm Rev G |
| C_xxxxb |
90 nm Rev F (in Fr3) |
| ...._xx00b |
Socket 754 or Socket S1 |
| ...._xx01b |
Socket 940 or Socket F1207 |
| ...._xx10b |
if Rev CG, then see K8 erratum #108 |
| ...._xx11b |
Socket 939 or Socket AM2 or ASB1 |
| ...._01xxb |
SH (SC 1024 KB) (Sledgehammer) |
| ...._11xxb |
DH (SC 512 KB) (Drillhammer) |
| ...._10xxb |
CH (SC 256 KB) (Clawhammer) |
| ...._00xxb |
JH (DC 1024 KB) (Jackhammer) |
| ...._10xxb |
BH (DC 512 KB) (Ballhammer) |
AMD K8L
(Fam 10h)
(Hound)
--------------------------
GH Greyhound
--------------------------
B. Barcelona
C. Shanghai
D. Istanbul
--------------------------
DR Deerhound
RB Ridgeback
BL Bloodhound
DA Dalmatian
HY Hydra
PH Pharaohound
--------------------------
|
0 |
Rev A DR (0=A0) (1=A1) (2=A2) |
| 2 |
Rev B DR (0=B0) (1=B1) (A=BA) (2=B2) (3=B3) |
| 4/5/6 |
Rev C RB/BL/DA (0=C0) (1=C1) (2=C2) (3=C3) |
| 8/9 |
Rev D HY SCM/MCM (0=D0) (1=D1) |
| A |
Rev E PH (0=E0) |
|
AMD K8
(Fam 11h) |
3 |
LG (1=B1) (Little Griffin) |
| |
AMD K8L
(Fam 12h) |
0 |
LN1 (0=A0) (1=A1) (Llano) |
| 1 |
LN1 (0=B0) |
| 2 |
LN2 (0=B0) |
| exotic extinct AMD processors |
AMD BC
(Fam 14h)
(Bobcat) |
0 |
ON (0=A0) (Ontario) |
| 1 |
ON (0=B0) |
| 2 |
ON (0=C0) |
AMD BD
(Fam 15h)
--------------------------
BD Bulldozer
PD Piledriver
SR Steamroller
XV Excavator
--------------------------
|
00 |
BD OR (0=A0) (1=A1) (Orochi) |
| 01 |
BD OR (0=B0) (1=B1) (2=B2) |
| 02 |
BD OR (0=C0) |
| 10 |
PD TN (1=A1) (Trinity) |
| 13 |
PD RL (1=A1) (Richland) |
| 30 |
SR KV (0=A0) (1=A1) (Kaveri) |
| 38 |
SR GV (1=A1) (Godavari) |
| 60 |
XV CZ (0=A0) (1=A1) (Carrizo) |
| 65 |
XV CZ (OSVW.ID5=0) (1=A1) (Carrizo) DDR4
XV BR (OSVW.ID5=1) (1=A1) (Bristol Ridge)
|
| 70 |
XV ST (0=A0) (Stoney Ridge) |
AMD JG
(Fam 16h)
(Jaguar) |
00 |
KB (0=A0) (1=A1) (Kabini) |
| 04 |
BV (1=A1) (Bhavani) |
| 26 |
Cato (1=A1) – see Xbox One (Durango 28nm) (DDR3) |
| 30 |
ML (0=A0) (1=A1) (Mullins) |
| 60 |
NL (1=A1) (Nolan) (not productized) |
| ?? |
348 mm2 SONY PS4 Fat (Liverpool 28nm) (GDDR5) |
| ?? |
209 mm2 SONY PS4 Slim (Liverpool 16nm) (GDDR5) |
| ?? |
322 mm2 SONY PS4 Pro (Neo 16nm) (GDDR5) |
| ?? |
363 mm2 MSFT Xbox One (Durango 28nm) (DDR3) |
| ?? |
240 mm2 MSFT Xbox One S (Edmonton 16nm) (DDR3) |
| ?? |
359 mm2 MSFT Xbox One X (Scorpio 16nm) (GDDR5) |
| contemporary AMD processors |
AMD Z1/Z2
(Fam 17h)
(c=classic d=dense x=mixed) |
00 |
Z1 ZP (Zeppelin) (EPYC Naples) (SP3) |
| 08 |
Z1 PR (Pinnacle Ridge) |
| 10 |
Z1 RV1 (Raven Ridge 1) |
| 18 |
Z1 PCO (Picasso) |
| 20 |
Z1 RV2 (Raven Ridge 2) |
| 30 |
Z2 SSP (Starship) (EPYC Rome) (SP3) |
| 47 |
Z2d 4700S (Cardinal🖱) (see PS5 – no GFX) (no ucode) |
| 50 |
Z1 Subor (Fenghuang/FireFlight) |
| 60 |
Z2 RN (Renoir) |
| 68 |
Z2 LCN (Lucienne) |
| 70 |
Z2 MTS (Matisse) |
| 84 |
Z2c 4800S (Ariel) (see Xbox Series X – no GFX) |
| 90 |
Z2 VN (Van Gogh) (Steam Deck) |
| 98 |
Z2 MR (Mero) (Magic Leap 2) (no ucode) |
| A0 |
MDN (Mendocino) |
| ?? |
308 mm2 SONY PS5 (Oberon 7nm) |
| ?? |
260 mm2 SONY PS5 (Oberon 6nm) |
| ?? |
279 mm2 SONY PS5 Pro (Viola 4nm) |
| ?? |
360 mm2 MSFT Xbox Series X (Anaconda 7nm) |
| ?? |
197 mm2 MSFT Xbox Series S (Lockhart 7nm) |
| ?? |
??? mm2 MSFT Xbox Series X (Anaconda 6nm) |
Hygon
(Fam 18h) |
0X |
Z1-derived (e.g. 64 KiB L1i and FP128)
Model 00 to Model 01 changes:
+PCLMUL +SHA +SME +SEV +VMPAGE_FLUSH +SEV-ES
11-bit PA redux and 15 guests
bug fix: reported L2 small page TLB ways (6 to 8)
bug fix: reported L2 large page TLB ways (3 to 2)
Model 01 to Model 02 changes:
+TSCD +ITSC
Model 02 to Model 04 changes:
unknown (no CPUID dump)
Model 04 to Model 06 changes:
unknown (no CPUID dump)
Model 06 to Model 07 changes:
unknown (no CPUID dump)
|
| 1X |
Z2-derived (e.g. 32 KiB L1i and FP256)
Model 0X to Model 10 changes:
changed L1 instruction cache (64 KiB to 32 KiB)
changed FP unit overall width (FP128 to FP256)
changed L2 small page TLB size (1536 to 2048)
changed L2 large page TLB size (1536 to 2048)
changed package type (6h to Bh)
+UMIP
+IBRS_ALL +STIBP_ALL +IBRS_PREF +SSBD
+SPEC_CTRL virtualization
–PAT (in extended leaf – bug due to confusion over history?)
–SEV (can't tell disabled-vs-removed from the CPUID dump)
|
AMD Z3/Z4
(Fam 19h)
(c=classic d=dense x=mixed) |
00 |
Z3 GN (Genesis) (EPYC Milan) (SP3) |
| 08 |
Z3 CGL (Chagall) (Threadripper using GN) |
| 10 |
Z4 RS (Rolling Stones) (EPYC Genoa) (SP5) (was Floyd) |
| 18 |
Z4 STP (Storm Peak) (Threadripper using RS) |
| 20 |
Z3 VMR (Vermeer) |
| 30 |
Z3 BA (Badami) (no ucode) |
| 40 |
Z3 RMB (Rembrandt) |
| 50 |
Z3 CZN (Cezanne) |
| 60 |
Z4 RPL (Raphael) |
| 70 |
Z4 PHX1 (Phoenix 1) (8c) |
| 74 |
Z4 PHX4 (Phoenix 4) (8c) |
| 75 |
Z4 HPT1 (Hawk Point 1) (8c) |
| 78 |
Z4x PHX2 (Phoenix 2) (2c+4c Z4c+Z4d) |
| 7C |
Z4x HPT2 (Hawk Point 2) (2c+4c Z4c+Z4d) |
| 80 |
Z4 MI300C (12xCCD=96c + 0xXCD=n/a) |
| 90 |
Z4 MI300A (3xCCD=24c + 6xXCD=228cu) |
| n/a |
–– MI300X (0xCCD=n/a + 8xXCD=304cu) |
| n/a |
–– MI300P (0xCCD=n/a + 4xXCD=152cu) |
| A0 |
Z4d RSDN (RS Dense) (EPYC Bergamo/Siena) (SP5/SP6) |
AMD Z5/Z6
(Fam 1Ah)
(c=classic d=dense x=mixed) |
00 |
Z5c BRH (Breithorn) (EPYC Turin/Sorano) (SP5/SP6) |
| 08 |
Z5c SHP (Shimada Peak) (Threadripper using BRH) |
| 10 |
Z5d BRHD (Breithorn Dense) (EPYC Turin Dense) (SP5) |
| 20 |
Z5x STX1 (Strix 1) (4c+8c Z5c+Z5d) |
| 30 |
Z5_ STX2 (Strix 2) (no ucode) |
| 38 |
Z5_ STX3 (Strix 3) (no ucode) |
| 40 |
Z5c GNR (Granite Ridge) (16c) |
| 50 |
Z6d WH (Weisshorn) (EPYC Venice Dense) (SP7 16-ch) |
| 60 |
Z5x KR1 (Krackan Point 1) (4c+4c Z5c+Z5d) |
| 68 |
Z5x KR2 (Krackan Point 2) (1c+3c Z5c+Z5d) |
| 70 |
Z5c STXH (Strix Halo) (2x 8c CCD) (Sarlak) |
| 80 |
Z6x ??? (Medusa) (4c+4c+2c Z6c+Z6d+Z6dLP) |
| 90 |
Z6d ??? (TBD) (EPYC Venice? Dense) (SP8 8-ch) |
| A0 |
Z6c ??? (TBD) (EPYC Venice?? Classic) (SP8 8-ch) |
| B0 |
Z6_ ??? (TBD) |
| C0 |
Z6c ??? (TBD) (EPYC Venice?? Classic) (SP7 16-ch) |
| D0 |
Z5_ ??? (Annapurna) (EPYC for NS) |
| D8 |
Z6_ ??? (TBD) |
AMD Z7
(Fam TBD) |
??
|
TBD
|
| stepping |
The stepping is encoded in bits 3...0. |
| The stepping values are processor-specific. |
| EBX=aall_ccbbh |
brand ID |
The brand ID is encoded in bits 7...0. |
| 00h |
not supported |
| 01h |
0.18 µm Intel Celeron |
| 02h |
0.18 µm Intel Pentium III |
| 03h |
0.18 µm Intel Pentium III Xeon if FMS != 6B1h |
| 03h |
0.13 µm Intel Celeron if FMS == 6B1h |
| 04h |
0.13 µm Intel Pentium III |
| 07h |
0.13 µm Intel Celeron mobile |
| 06h |
0.13 µm Intel Pentium III mobile |
| 0Ah |
0.18 µm Intel Celeron 4 |
| 08h |
0.18 µm Intel Pentium 4 if FMS != F24h |
| 09h |
0.13 µm Intel Pentium 4 |
| 0Eh |
0.18 µm Intel Pentium 4 Xeon if FMS == F13h |
| 0Bh |
0.18 µm Intel Pentium 4 Xeon MP if FMS == F13h |
| 0Bh |
0.13 µm Intel Pentium 4 Xeon if FMS != F13h |
| 0Ch |
0.13 µm Intel Pentium 4 Xeon MP |
| 08h |
0.13 µm Intel Celeron 4 mobile if FMS == F24h |
| 0Fh |
0.13 µm Intel Celeron 4 mobile if FMS == F27h |
| 0Eh |
0.13 µm Intel Pentium 4 mobile (prod.) if FMS != F13h |
| 0Fh |
0.13 µm Intel Pentium 4 mobile (samp.) if FMS != F27h |
| 11h |
mobile Intel ??? processor |
| 12h |
0.13 µm Intel Celeron M |
| 12h |
0.09 µm Intel Celeron M |
| 13h |
mobile Intel Celeron ? processor |
| 14h |
Intel Celeron ? processor |
| 15h |
mobile Intel ??? processor |
| 16h |
0.13 µm Intel Pentium M |
| 16h |
0.09 µm Intel Pentium M |
| 17h |
mobile Intel Celeron ? processor |
| AMD |
see extended leaf 8000_0001h
with ID=0000_0765_0000_0000b and NN=4_3210b
|
| CLFLUSH |
The CLFLUSH (8-byte) chunk count is encoded in bits 15...8. |
| CPU count |
The logical processor count is encoded in bits 23...16. |
| APIC ID |
The (fixed) default APIC ID is encoded in bits 31...24. |
| ECX=xxxx_xxxxh |
feature flags |
description |
| 31 (HV) |
hypervisor present (and intercepting this bit, to advertise its presence) |
| 30 (RDRAND) |
RDRAND |
| 29 (F16C) |
VCVTPH2PS and VCVTPS2PH |
| 28 (AVX) |
AVX |
| 27 (OSXSAVE) |
non-privileged read-only copy of current CR4.OSXSAVE value |
| 26 (XSAVE) |
CR4.OSXSAVE, XCRn, XGETBV, XSETBV, XSAVE(OPT), XRSTOR
also see standard leaf 0000_000Dh
|
| 25 (AES) |
AES* |
| 24 (TSCD) |
local APIC supports one-shot operation using TSC deadline value |
| 23 (POPCNT) |
POPCNT |
| 22 (MOVBE) |
MOVBE |
| 21 (x2APIC) |
x2APIC, APIC_BASE.EXTD, MSRs 0000_0800h...0000_0BFFh
64-bit ICR (+030h but not +031h), no DFR (+00Eh), SELF_IPI (+040h)
also see standard leaf 0000_000Bh
|
| 20 (SSE4.2) |
SSE4.2 |
| 19 (SSE4.1) |
SSE4.1, MXCSR, CR4.OSXMMEXCPT, #XF |
| 18 (DCA) |
Direct Cache Access (that is, the ability to prefetch data from MMIO)
also see standard leaf 0000_0009h
|
| 17 (PCID) |
CR4.PCIDE |
| 16 |
reserved |
| 15 (PDCM) |
Performance Debug Capability MSR |
| 14 (ETPRD) |
MISC_ENABLE.ETPRD |
| 13 (CX16) |
CMPXCHG16B |
| 12 (FMA) |
FMA |
| 11 (SDBG) |
DEBUG_INTERFACE MSR for silicon debug |
| 10 (CID) |
context ID: the L1 data cache can be set to adaptive or shared mode
MISC_ENABLE.L1DCCM
|
| 9 (SSSE3) |
SSSE3 |
| 8 (TM2) |
MISC_ENABLE.TM2E
THERM_INTERRUPT and THERM_STATUS MSRs
xAPIC thermal LVT entry
THERM2_CONTROL MSR
|
| 7 (EST) |
Enhanced SpeedStep Technology |
| 6 (SMX) |
CR4.SMXE, GETSEC |
| 5 (VMX) |
CR4.VMXE, VM* and VM* |
| 4 (DSCPL) |
CPL-qualified Debug Store |
| 3 (MON) |
MONITOR/MWAIT, MISC_ENABLE.MONE, MISC_ENABLE.LCMV
MONITOR_FILTER_LINE_SIZE MSR
also see standard leaf 0000_0005h
setting MISC_ENABLE.MONE=0 causes MON=0
|
| 2 (DTES64) |
64-bit Debug Trace and EMON Store MSRs |
| 1 (PCLMUL) |
PCLMULQDQ |
| 0 (SSE3) |
SSE3, MXCSR, CR4.OSXMMEXCPT, #XF, if FPU=1 then also FISTTP |
| EDX=xxxx_xxxxh |
feature flags |
description |
| 31 (PBE) |
Pending Break Event, STPCLK, FERR#, MISC_ENABLE.PBE |
| 30 (IA-64) |
IA-64, JMPE Jv, JMPE Ev |
| 29 (TM1) |
MISC_ENABLE.TM1E
THERM_INTERRUPT and THERM_STATUS MSRs
xAPIC thermal LVT entry
|
| 28 (HTT) |
Hyper-Threading Technology, PAUSE |
| 27 (SS) |
selfsnoop |
| 26 (SSE2) |
SSE2, MXCSR, CR4.OSXMMEXCPT, #XF |
| 25 (SSE) |
SSE, MXCSR, CR4.OSXMMEXCPT, #XF |
| 24 (FXSR) |
FXSAVE/FXRSTOR, CR4.OSFXSR |
| 23 (MMX) |
MMX |
| 22 (ACPI) |
THERM_CONTROL MSR |
| 21 (DTES) |
Debug Trace and EMON Store MSRs |
| 20 |
reserved |
| 19 (CLFL) |
CLFLUSH |
| 18 (PSN) |
PSN (see standard leaf 0000_0003h), PSN_CTL.PSND #1 |
| 17 (PSE36) |
4 MB PDE bits 16...13, CR4.PSE |
| 16 (PAT) |
PAT MSR, PDE/PTE.PAT |
| 15 (CMOV) |
CMOVcc, if FPU=1 then also FCMOVcc/F(U)COMI(P) |
| 14 (MCA) |
MCG_*/MCn_* MSRs, CR4.MCE, #MC |
| 13 (PGE) |
PDE/PTE.G, CR4.PGE |
| 12 (MTRR) |
MTRR* MSRs |
| 11 (SEP) |
SYSENTER/SYSEXIT, SEP_* MSRs #2 |
| 10 |
reserved |
| 9 (APIC) |
APIC #3, #4 |
| 8 (CX8) |
CMPXCHG8B #5 |
| 7 (MCE) |
MCAR/MCTR MSRs, CR4.MCE, #MC |
| 6 (PAE) |
64-bit PDPTE/PDE/PTEs, CR4.PAE |
| 5 (MSR) |
MSRs, RDMSR/WRMSR |
| 4 (TSC) |
TSC, RDTSC, CR4.TSD (doesn't imply MSR=1) |
| 3 (PSE) |
PDE.PS, PDE/PTE.res, CR4.PSE, #PF(1xxxb) |
| 2 (DE) |
CR4.DE, DR7.RW=10b, #UD on MOV from/to DR4/5 |
| 1 (VME) |
CR4.VME/PVI, EFLAGS.VIP/VIF, TSS32.IRB |
| 0 (FPU) |
FPU |
|
| notes |
descriptions |
|
| #1 |
If the PSN has been disabled, then the PSN feature flag will read as 0. In addition the value for the maximum
supported standard leaf (reported by standard leaf 0000_0000h, register EAX) will be lower.
|
| #2 |
The Intel P6 processor does not support SEP, but inadvertently reports it. |
| #3 |
If the APIC has been disabled, then the APIC feature flag will read as 0. |
| #4 |
Early AMD K5 processors (SSA5) inadvertently used this bit to report PGE support. |
| #5 |
Some processors do support CMPXCHG8B, but don't report it by default. This is due to a Windows NT bug. |
standard leaf 0000_0002h
|
|
| input |
EAX=0000_0002h |
get processor configuration descriptors |
|
| output |
AL |
number of times this leaf must be queried to obtain all configuration descriptors #1 |
EAX.15...8
EAX.23...16
EAX.31...24
EBX.0...7
EBX.15...8
EBX.23...16
EBX.31...24
ECX.0...7
ECX.15...8
ECX.23...16
ECX.31...24
EDX.0...7
EDX.15...8
EDX.23...16
EDX.31...24
|
configuration descriptors #2 |
| value |
description |
| 00h |
null descriptor (=unused descriptor) |
| 01h |
code TLB, 4K pages, 4 ways, 32 entries |
| 02h |
code TLB, 4M pages, fully, 2 entries |
| 03h |
data TLB, 4K pages, 4 ways, 64 entries |
| 04h |
data TLB, 4M pages, 4 ways, 8 entries |
| 05h |
data TLB, 4M pages, 4 ways, 32 entries |
| 06h |
code L1 cache, 8 KB, 4 ways, 32 byte lines |
| 08h |
code L1 cache, 16 KB, 4 ways, 32 byte lines |
| 09h |
code L1 cache, 32 KB, 4 ways, 64 byte lines |
| 0Ah |
data L1 cache, 8 KB, 2 ways, 32 byte lines |
| 0Bh |
code TLB, 4M pages, 4 ways, 4 entries |
| 0Ch |
data L1 cache, 16 KB, 4 ways, 32 byte lines |
| 0Dh |
data L1 cache, 16 KB, 4 ways, 64 byte lines (ECC) |
| 0Eh |
data L1 cache, 24 KB, 6 ways, 64 byte lines |
| 10h |
data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64) |
| 15h |
code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64) |
| 1Ah |
code and data L2 cache, 96 KB, 6 ways, 64 byte lines (IA-64) |
| 1Dh |
code and data L2 cache, 128 KB, 2 ways, 64 byte lines |
| 21h |
code and data L2 cache, 256 KB, 8 ways, 64 byte lines |
| 22h |
code and data L3 cache, 512 KB, 4 ways, 64 byte lines, dual-sectored |
| 23h |
code and data L3 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored |
| 24h |
code and data L2 cache, 1024 KB, 16 ways, 64 byte lines |
| 25h |
code and data L3 cache, 2048 KB, 8 ways, 64 byte lines, dual-sectored |
| 29h |
code and data L3 cache, 4096 KB, 8 ways, 64 byte lines, dual-sectored |
| 2Ch |
data L1 cache, 32 KB, 8 ways, 64 byte lines |
| 30h |
code L1 cache, 32 KB, 8 ways, 64 byte lines |
| 39h |
code and data L2 cache, 128 KB, 4 ways, 64 byte lines, sectored |
| 3Ah |
code and data L2 cache, 192 KB, 6 ways, 64 byte lines, sectored |
| 3Bh |
code and data L2 cache, 128 KB, 2 ways, 64 byte lines, sectored |
| 3Ch |
code and data L2 cache, 256 KB, 4 ways, 64 byte lines, sectored |
| 3Dh |
code and data L2 cache, 384 KB, 6 ways, 64 byte lines, sectored |
| 3Eh |
code and data L2 cache, 512 KB, 4 ways, 64 byte lines, sectored |
| 40h |
no integrated L2 cache (P6 core) or L3 cache (P4 core) |
| 41h |
code and data L2 cache, 128 KB, 4 ways, 32 byte lines |
| 42h |
code and data L2 cache, 256 KB, 4 ways, 32 byte lines |
| 43h |
code and data L2 cache, 512 KB, 4 ways, 32 byte lines |
| 44h |
code and data L2 cache, 1024 KB, 4 ways, 32 byte lines |
| 45h |
code and data L2 cache, 2048 KB, 4 ways, 32 byte lines |
| 46h |
code and data L3 cache, 4096 KB, 4 ways, 64 byte lines |
| 47h |
code and data L3 cache, 8192 KB, 8 ways, 64 byte lines |
| 48h |
code and data L2 cache, 3072 KB, 12 ways, 64 byte lines |
| 49h |
code and data L3 cache, 4096 KB, 16 ways, 64 byte lines (P4) or
code and data L2 cache, 4096 KB, 16 ways, 64 byte lines (Core 2)
|
| 4Ah |
code and data L3 cache, 6144 KB, 12 ways, 64 byte lines |
| 4Bh |
code and data L3 cache, 8192 KB, 16 ways, 64 byte lines |
| 4Ch |
code and data L3 cache, 12288 KB, 12 ways, 64 byte lines |
| 4Dh |
code and data L3 cache, 16384 KB, 16 ways, 64 byte lines |
| 4Eh |
code and data L2 cache, 6144 KB, 24 ways, 64 byte lines |
| 4Fh |
code TLB, 4K pages, ???, 32 entries |
| 50h |
code TLB, 4K/4M/2M pages, fully, 64 entries |
| 51h |
code TLB, 4K/4M/2M pages, fully, 128 entries |
| 52h |
code TLB, 4K/4M/2M pages, fully, 256 entries |
| 55h |
code TLB, 2M/4M, fully, 7 entries |
| 56h |
L0 data TLB, 4M pages, 4 ways, 16 entries |
| 57h |
L0 data TLB, 4K pages, 4 ways, 16 entries |
| 59h |
L0 data TLB, 4K pages, fully, 16 entries |
| 5Ah |
L0 data TLB, 2M/4M, 4 ways, 32 entries |
| 5Bh |
data TLB, 4K/4M pages, fully, 64 entries |
| 5Ch |
data TLB, 4K/4M pages, fully, 128 entries |
| 5Dh |
data TLB, 4K/4M pages, fully, 256 entries |
| 60h |
data L1 cache, 16 KB, 8 ways, 64 byte lines, sectored |
| 61h |
code TLB, 4K pages, fully, 48 entries |
| 63h |
data TLB, 2M/4M pages, 4-way, 32-entries, and
data TLB, 1G pages, 4-way, 4 entries
|
| 64h |
data TLB, 4K pages, 4-way, 512 entries |
| 66h |
data L1 cache, 8 KB, 4 ways, 64 byte lines, sectored |
| 67h |
data L1 cache, 16 KB, 4 ways, 64 byte lines, sectored |
| 68h |
data L1 cache, 32 KB, 4 ways, 64 byte lines, sectored |
| 6Ah |
L0 data TLB, 4K pages, 8-way, 64 entries |
| 6Bh |
data TLB, 4K pages, 8-way, 256 entries |
| 6Ch |
data TLB, 2M/4M pages, 8-way, 128 entries |
| 6Dh |
data TLB, 1G pages, fully, 16 entries |
| 70h |
trace L1 cache, 12 KµOPs, 8 ways |
| 71h |
trace L1 cache, 16 KµOPs, 8 ways |
| 72h |
trace L1 cache, 32 KµOPs, 8 ways |
| 73h |
trace L1 cache, 64 KµOPs, 8 ways |
| 76h |
code TLB, 2M/4M pages, fully, 8 entries |
| 77h |
code L1 cache, 16 KB, 4 ways, 64 byte lines, sectored (IA-64) |
| 78h |
code and data L2 cache, 1024 KB, 4 ways, 64 byte lines |
| 79h |
code and data L2 cache, 128 KB, 8 ways, 64 byte lines, dual-sectored |
| 7Ah |
code and data L2 cache, 256 KB, 8 ways, 64 byte lines, dual-sectored |
| 7Bh |
code and data L2 cache, 512 KB, 8 ways, 64 byte lines, dual-sectored |
| 7Ch |
code and data L2 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored |
| 7Dh |
code and data L2 cache, 2048 KB, 8 ways, 64 byte lines |
| 7Eh |
code and data L2 cache, 256 KB, 8 ways, 128 byte lines, sect. (IA-64) |
| 7Fh |
code and data L2 cache, 512 KB, 2 ways, 64 byte lines |
| 80h |
code and data L2 cache, 512 KB, 8 ways, 64 byte lines |
| 81h |
code and data L2 cache, 128 KB, 8 ways, 32 byte lines |
| 82h |
code and data L2 cache, 256 KB, 8 ways, 32 byte lines |
| 83h |
code and data L2 cache, 512 KB, 8 ways, 32 byte lines |
| 84h |
code and data L2 cache, 1024 KB, 8 ways, 32 byte lines |
| 85h |
code and data L2 cache, 2048 KB, 8 ways, 32 byte lines |
| 86h |
code and data L2 cache, 512 KB, 4 ways, 64 byte lines |
| 87h |
code and data L2 cache, 1024 KB, 8 ways, 64 byte lines |
| 88h |
code and data L3 cache, 2048 KB, 4 ways, 64 byte lines (IA-64) |
| 89h |
code and data L3 cache, 4096 KB, 4 ways, 64 byte lines (IA-64) |
| 8Ah |
code and data L3 cache, 8192 KB, 4 ways, 64 byte lines (IA-64) |
| 8Dh |
code and data L3 cache, 3072 KB, 12 ways, 128 byte lines (IA-64) |
| 90h |
code TLB, 4K...256M pages, fully, 64 entries (IA-64) |
| 96h |
data L1 TLB, 4K...256M pages, fully, 32 entries (IA-64) |
| 9Bh |
data L2 TLB, 4K...256M pages, fully, 96 entries (IA-64) |
| A0h |
data TLB, 4K pages, fully, 32 entries |
| B0h |
code TLB, 4K pages, 4 ways, 128 entries |
| B1h |
code TLB, 4M pages, 4 ways, 4 entries and
code TLB, 2M pages, 4 ways, 8 entries
|
| B2h |
code TLB, 4K pages, 4 ways, 64 entries |
| B3h |
data TLB, 4K pages, 4 ways, 128 entries |
| B4h |
data TLB, 4K pages, 4 ways, 256 entries |
| B5h |
code TLB, 4K pages, 8 ways, 64 entries |
| B6h |
code TLB, 4K pages, 8 ways, 128 entries |
| BAh |
data TLB, 4K pages, 4 ways, 64 entries |
| C0h |
data TLB, 4K/4M pages, 4 ways, 8 entries |
| C1h |
L2 code and data TLB, 4K/2M pages, 8 ways, 1024 entries |
| C2h |
data TLB, 2M/4M pages, 4 ways, 16 entries
|
|
2M/4M in Sep 2013 version of this page |
|
The SDM almost got it right at first... but then... |
| 2M/4M in Sep 2013 22nm AVN BWG (correct) |
2M/$M in Sep 2013 SDM 048 ('$' shift typo '4') (close) |
| 2M/4M in Sep 2013 22nm BYT BWG (correct) |
4K/2M in Feb 2014 SDM 049 (bad correction attempt) |
| 2M/4M in Aug 2017 14nm DVN SU (correct) |
4K/2M in Feb 2026 SDM 090 (12 years later: still bad) |
| |
2M/4M in Mar 2026 SDM 091 (fixed after I reported it) |
|
|
| C3h |
L2 code and data TLB, 4K/2M pages, 6 ways, 1536 entries and
L2 code and data TLB, 1G pages, 4 ways, 16 entries
|
| C4h |
data TLB, 2M/4M pages, 4-way, 32 entries |
| CAh |
L2 code and data TLB, 4K pages, 4 ways, 512 entries |
| D0h |
code and data L3 cache, 512 KB, 4 ways, 64 byte lines |
| D1h |
code and data L3 cache, 1024 KB, 4 ways, 64 byte lines |
| D2h |
code and data L3 cache, 2048 KB, 4 ways, 64 byte lines |
| D6h |
code and data L3 cache, 1024 KB, 8 ways, 64 byte lines |
| D7h |
code and data L3 cache, 2048 KB, 8 ways, 64 byte lines |
| D8h |
code and data L3 cache, 4096 KB, 8 ways, 64 byte lines |
| DCh |
code and data L3 cache, 1536 KB, 12 ways, 64 byte lines |
| DDh |
code and data L3 cache, 3072 KB, 12 ways, 64 byte lines |
| DEh |
code and data L3 cache, 6144 KB, 12 ways, 64 byte lines |
| E2h |
code and data L3 cache, 2048 KB, 16 ways, 64 byte lines |
| E3h |
code and data L3 cache, 4096 KB, 16 ways, 64 byte lines |
| E4h |
code and data L3 cache, 8192 KB, 16 ways, 64 byte lines |
| EAh |
code and data L3 cache, 12288 KB, 24 ways, 64 byte lines |
| EBh |
code and data L3 cache, 18432 KB, 24 ways, 64 byte lines |
| ECh |
code and data L3 cache, 24576 KB, 24 ways, 64 byte lines |
| F0h |
64 byte prefetching |
| F1h |
128 byte prefetching |
| FEh |
query standard leaf 0000_0018h instead |
| FFh |
query standard leaf 0000_0004h instead |
| value |
description |
| 70h |
Cyrix specific: code and data TLB, 4K pages, 4 ways, 32 entries |
| 74h |
Cyrix specific: ??? |
| 77h |
Cyrix specific: ??? |
| 80h |
Cyrix specific: code and data L1 cache, 16 KB, 4 ways, 16 byte lines |
| 82h |
Cyrix specific: ??? |
| 84h |
Cyrix specific: ??? |
| value |
description |
| others |
reserved |
example
(here: P6) |
EAX=0302_0101h
EBX=0000_0000h
ECX=0000_0000h
EDX=0604_0A43h
|
Because AL is 01h, one invocation of the leaf is enough to obtain all the
configuration descriptors. All of them are valid because their highest bits
are zero. This P6 processor includes a 4K/M code/data TLB, an 8+8 KB
code/data L1 cache and an integrated 512 KB code and data L2 cache.
|
|
| notes |
descriptions |
|
| #1 |
In a MP system special precautions must be taken when executing standard leaf 0000_0002h more than once.
In particular it must be ensured that the same CPU is used during that entire process. No processor has ever reported AL > 1.
|
| #2 |
Programs must not expect any particular order for the reported configuration descriptors. |
standard leaf 0000_0003h
|
|
| input |
EAX=0000_0003h |
get processor serial number #1 |
|
| output |
EAX=xxxx_xxxxh |
processor serial number (Transmeta Efficeon processors only) |
| EBX=xxxx_xxxxh |
processor serial number (Transmeta Crusoe and Efficeon processors only) |
| ECX=xxxx_xxxxh |
processor serial number |
| EDX=xxxx_xxxxh |
processor serial number |
|
| note |
description |
|
| #1 |
This leaf is only supported and enabled if the PSN feature flag is set. The reported processor serial number should be
combined with the vendor ID string and the processor type/family/model/stepping value, to distinguish cases in which
two processors from different vendors happen to have the same serial number. Finally, it should be noted that most of
the vendors can not guarantee that their serial numbers are truely unique.
|
standard leaf 0000_0004h
|
|
| input |
EAX=0000_0004h |
get cache configuration descriptors #1 |
| ECX=xxxx_xxxxh |
cache level to query (e.g. 0=L1D, 1=L2, or 0=L1D, 1=L1I, 2=L2) |
|
| output |
EAX |
bits |
description |
| 31...26 |
cores per package - 1 |
| 25...14 |
threads per cache - 1 |
| 13...10 |
reserved |
| 9 |
fully associative? |
| 8 |
self-initializing? |
| 7...5 |
cache level (starts at 1) |
| 4...0 |
cache type (0=null, 1=data, 2=code, 3=unified, 4...31=reserved) |
| EBX |
bits |
description |
| 31...22 |
ways of associativity - 1 |
| 21...12 |
physical line partitions - 1 |
| 11...0 |
system coherency line size - 1 |
| ECX |
bits |
description |
| 31...0 |
sets - 1 |
| EDX |
bits |
description |
| 31...3 |
reserved |
| 2 |
complex indexing? |
| 1 |
inclusive of lower levels? |
| 0 |
write-back invalidate? |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0005h
|
|
| input |
EAX=0000_0005h |
get MON information #1 |
|
| output |
EAX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
smallest monitor line size in bytes |
| EBX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
largest monitor line size in bytes |
| ECX |
bits |
description |
| 31...4 |
reserved |
| 3 |
MONITOR-less MWAIT |
| 2 |
reserved |
| 1 |
treat interrupts as break events, even when interrupts are disabled |
| 0 |
enumeration of MWAIT extensions (beyond EAX and EBX) |
| EDX |
bits |
description |
| 31...28 |
number of C7 sub C-states for MWAIT |
| 27...24 |
number of C6 sub C-states for MWAIT |
| 23...20 |
number of C5 sub C-states for MWAIT |
| 19...16 |
number of C4 sub C-states for MWAIT (starting with Core 7: C7) |
| 15...12 |
number of C3 sub C-states for MWAIT (starting with Core 7: C6) |
| 11...8 |
number of C2 sub C-states for MWAIT |
| 7...4 |
number of C1 sub C-states for MWAIT |
| 3...0 |
number of C0 sub C-states for MWAIT |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0006h
|
|
| input |
EAX=0000_0006h |
get power management information #1 |
|
| output |
EAX |
bits |
description |
| 31...25 |
reserved |
| 24 |
THERM_INTERRUPT MSR bit 25 (SDM 078 to SDM 087) |
| 23 |
thread director |
| 22 |
HWP_CTL MSR |
| 21 |
reserved |
| 20 |
ignore idle logical processor HWP request |
| 19 |
HW feedback |
| 18 |
HWP_REQUEST MSR is low-latency and posted-write |
| 17 |
HWP thread request |
| 16 |
HWP PECI |
| 15 |
HWP highest change notification |
| 14 |
favorite core (aka turbo max 3.0) |
| 13 (HDC) |
PKG_HDC_CTL, PM_CTL1, and THREAD_STALL MSRs |
| 12 |
reserved |
| 11 (HWP_PLR) |
HWP_REQUEST_PKG MSR |
| 10 (HWP_EPP) |
HWP_REQUEST MSR bits 31...24 |
| 9 (HWP_ACT) |
HWP_REQUEST MSR bits 41...32 |
| 8 (HWP_NOT) |
HWP_INTERRUPT MSR |
| 7 (HWP) |
PM_ENABLE bit 0, HWP_{CAPABILITIES,REQUEST,STATUS} MSRs |
| 6 (PTM) |
PACKAGE_THERMAL_STATUS MSR |
| 5 (ECMD) |
CLOCK_MODULATION MSR |
| 4 (PLN) |
THERM_STATUS MSR bits 10/11
THERM_INTERRUPT MSR bit 24
|
| 3 |
reserved |
2 (ARAT)
2 (OPP) |
always running APIC timer (in every C-state and regardless of P-state)
P4: operating point protection (protect CPU's ratio/VID points) #2 |
| 1 (DA) |
dynamic acceleration (MISC.ENABLE.DAD=0) |
| 0 (DTS) |
digital thermal sensor |
| EBX |
bits |
description |
| 31...4 |
reserved |
| 3...0 |
number of programmable digital thermal sensor interrupt thresholds |
| ECX |
bits |
description |
| 31...16 |
reserved |
| 15...8 |
HW feedback number of classes |
| 7...4 |
reserved |
| 3 |
ENERGY_PERF_BIAS MSR (0000_01B0h) |
| 2 |
reserved |
| 1 |
ACNT2 |
| 0 |
MPERF/APERF |
| EDX |
bits |
description |
| 31...16 |
HW feedback table index |
| 15...12 |
reserved |
| 11...8 |
HW feedback table size |
| 7...2 |
reserved for future capabilities |
| 1 |
energy efficiency capability reporting supported |
| 0 |
performance capability reporting supported |
|
| notes |
descriptions |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
| #2 |
The implementation of OPP is processor and stepping specific.
On certain Pentium 4 processors, the protection mechanism is Snap-to-VID and it is enabled if the bit is set.
|
standard leaf 0000_0007h
|
|
| input |
EAX=0000_0007h |
get feature flags #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n as per EAX reported by sub-leaf 0) |
|
output
(sub 0) |
EAX |
bits |
description |
| 31...0 |
max sub-leaf |
| EBX |
bits |
description |
| 31 (AVX512VL) |
AVX512VL |
| 30 (AVX512BW) |
AVX512BW |
| 29 (SHA) |
SHA |
| 28 (AVX512CD) |
AVX512CD |
| 27 (AVX512ER) |
AVX512ER |
| 26 (AVX512PF) |
AVX512PF |
| 25 (PT) |
processor trace, standard leaf 0000_0014h |
| 24 (CLWB) |
CLWB |
| 23 (CLFLUSHOPT) |
CLFLUSHOPT |
| 22 (PCOMMIT) |
PCOMMIT |
| 21 (AVX512IFMA) |
AVX512IFMA |
| 20 (SMAP) |
CR4.SMAP, CLAC and STAC |
| 19 (ADX) |
ADCX and ADOX |
| 18 (RDSEED) |
RDSEED |
| 17 (AVX512DQ) |
AVX512DQ |
| 16 (AVX512F) |
AVX512F, EVEX, ZMM0...31, K0...7, modifiers, VSIB512, disp8*N |
| 15 (RDT_A) |
RDT-A QoS allocation, standard leaf 0000_0010h |
| 14 (MPX) |
XCR0.Breg, XCR0.BNDCSR, BNDCFGS/BNDCFGU/BNDSTATUS and
BND0...BND3, BND:, MPX
|
| 13 (FPCSDS) |
FP_CS and FP_DS always saved as 0000h |
| 12 (RDT_M) |
RDT-M QoS monitoring, standard leaf 0000_000Fh |
| 11 (RTM) |
XBEGIN, XABORT, XEND, XTEST, DR7.RTM, DR6.RTM |
| 10 (INVPCID) |
INVPCID |
| 9 (ERMS) |
enhanced REP MOVSB/STOSB (while MISC_ENABLE.FSE=1) |
| 8 (BMI2) |
BMI2 |
| 7 (SMEP) |
CR4.SMEP |
| 6 (FPDP) |
FP_DP for non-control instructions only if unmasked exception(s) |
| 5 (AVX2) |
AVX2 (including VSIB) |
| 4 (HLE) |
XACQUIRE:, XRELEASE:, XTEST |
| 3 (BMI1) |
BMI1 and TZCNT |
| 2 (SGX) |
CR4.SEE, PRMRR, ENCLS and ENCLU, standard leaf 0000_0012h |
| 1 (TSC_ADJUST) |
TSC_ADJUST |
| 0 (FSGSBASE) |
CR4.FSGSBASE and [RD|WR][FS|GS]BASE |
| ECX |
bits |
description |
| 31 (PKS) |
protection keys for supervisor |
| 30 (SGX_LC) |
SGX launch configuration |
| 29 (ENQCMD) |
ENQCMD, ENQCMDS, and PASID |
| 28 (MOVDIR64B) |
MOVDIR64B |
| 27 (MOVDIRI) |
MOVDIRI |
| 26 (MPRR) |
Memory Protection Range Registers |
| 25 (CLDEMOTE) |
CLDEMOTE |
| 24 (BUS_LOCK_D.) |
bus lock detection, DEBUGCTL.BLD[2], DR6.BLD |
| 23 (KL) |
Key Locker, standard leaf 0000_0019h |
| 22 (RDPID) |
RDPID, TSC_AUX |
| 21 (MAWAU) |
MPX address-width adjust for CPL=3 |
| 20 (MAWAU) |
MPX address-width adjust for CPL=3 |
| 19 (MAWAU) |
MPX address-width adjust for CPL=3 |
| 18 (MAWAU) |
MPX address-width adjust for CPL=3 |
| 17 (MAWAU) |
MPX address-width adjust for CPL=3 |
| 16 (VA57) |
5-level paging, CR4.VA57 |
| 15 (FZM) |
Fast Zero Memory |
14 (AVX512VP...DQ)
14 (AVX512DFMA)
|
VPOPCNT{D,Q}
VDF{,N}MADD{SS,SD,PS,PD} – specified but didn't ship (KNH)
|
| 13 (TME) |
TME |
| 12 (AVX512BITALG) |
VPOPCNT{B,W} and VPSHUFBITQMB |
| 11 (AVX512VNNI) |
VPDP{BUS,WSS}D[S] |
| 10 (VPCL) |
VPCLMULQDQ (VEX.256 and EVEX) |
| 9 (VAES) |
VAES{ENC,DEC}{,LAST} (VEX.256 and EVEX) |
| 8 (GFNI) |
[V]GF2P8AFFINE{,INV}QB and [V]GF2P8MULB (SSE, VEX, and EVEX) |
| 7 (CET_SS) |
CR4.CET, XSS.CET_{U,S}, {U,S}_CET MSRs, PL{0,1,2,3}_SSP MSRs,
IST_SSP MSR and 8-entry interrupt SSP table, #CP, SSP, TSS32.SSP,
INCSSP, RDSSP, SAVESSP, RSTORSSP, SETSSBSY, CLRSSBSY,
WRSS, WRUSS, ENDBR32, ENDBR64, CALL/JMP Rv + no track (3Eh)
|
| 6 (AVX512VBMI2) |
VP{EXPAND,COMPRESS}{B,W} and VP{SHL,SHR}D{,V}{W,D,Q} |
| 5 (WAITPKG) |
UMONITOR, UMWAIT, TPAUSE |
| 4 (OSPKE) |
non-privileged read-only copy of current CR4.PKE value |
| 3 (PKU) |
XCR0.PKRU, CR4.PKE, PKRU, RDPKRU/WRPKRU, PxE.PK, #PF.PK |
| 2 (UMIP) |
CR4.UMIP for #GP on SGDT, SIDT, SLDT, STR, and SMSW if CPL>0 |
| 1 (AVX512VBMI) |
AVX512VBMI |
| 0 (PREFETCHWT1) |
PREFETCHWT1 |
| EDX |
bits |
description |
| 31 (SSBD) |
SPEC_CTRL.SSBD |
| 30 (CORE_CAP) |
CORE_CAPABILITIES MSR |
| 29 (ARCH_CAP) |
ARCH_CAPABILITIES MSR |
| 28 (L1D_FLUSH) |
FLUSH_CMD.L1D_FLUSH |
| 27 (STIBP) |
SPEC_CTRL.STIBP |
| 26 (IBRS_IBPB) |
SPEC_CTRL.IBRS and PRED_CMD.IBPB |
| 25 (AMX_INT8) |
AMX_INT8 |
| 24 (AMX_TILE) |
AMX_TILE |
| 23 (AVX512FP16) |
AVX512FP16 |
| 22 (AMX_BF16) |
AMX_BF16 |
| 21 |
reserved |
| 20 (CET_IBS) |
CET ENDBRANCH |
| 19 (ARCH_LBRS) |
architectural LBRs |
| 18 (PCONFIG) |
PCONFIG (for MK-TME) |
| 17 |
reserved |
| 16 (TSXLDTRK) |
non-transactional loads |
| 15 (HYBRID) |
hybrid part |
| 14 (SERIALIZE) |
SERIALIZE |
| 13 (RTM_F_ABORT) |
TSX_FORCE_ABORT.RTM_FORCE_ABORT |
| 12 |
reserved |
| 11 (RTM_A_ABORT) |
RTM_ALWAYS_ABORT |
| 10 (MD_CLEAR) |
MD_CLEAR (VERW Mw, FLUSH_CMD MSR, RSM, SGX entry/exit) |
| 9 (MCU_OPT_CTRL) |
MCU_OPT_CTRL MSR |
| 8 (AVX512VP2I...) |
VP2INTERSECT{D,Q} |
| 7 (AVX512BITALG2) |
VPADD[U]S{D,Q}
VPTERNLOG{B,W}
VPLZCNT{B,W}
VPTZCNT{B,W,D,Q} – specified but didn't ship (GLC)
|
| 6 |
reserved |
| 5 (UINTR) |
user interrupts |
| 4 (FSREPMOVSB) |
fast short REP MOVSB |
| 3 (AVX512QFMA) |
V4F[N]MADD{PS,SS} |
2 (AVX512QVNNIW)
(AVX512QVNNI) |
VP4DPWSSD[S]
VP4DPBUSD[S] – specified but didn't ship (KNM) |
| 1 (SGX_KEYS) |
SGX server style attestation |
| 0 (SGX_TEM) |
SGX Trusted Execution Mode |
|
output
(sub 1) |
EAX |
bits |
description |
| 31 (MOVRS) |
MOVRS |
| 30 (INVD_DIS) |
INVD can be disabled after BIOS completion |
| 29 |
reserved |
| 28 |
reserved |
| 27 (MSRLIST) |
RDMSRLIST/WRMSRLIST, BARRIER MSR |
| 26 (LAM) |
Linear Address Masking |
| 25 |
reserved |
| 24 |
reserved |
| 23 (AVX_IFMA) |
AVX_IFMA |
| 22 (HRESET) |
HRESET, HRESET_ENABLE MSR, standard leaf 0000_0020h |
| 21 (AMX_FP16) |
AMX_FP16 |
| 20 (NMI_SOURCE) |
NMI_SOURCE – optional extension of FRED, for a 16-bit LATCH_NMI |
| 19 (WRMSRNS) |
WRMSRNS |
| 18 (LKGS) |
LKGS |
| 17 (FRED) |
FRED – CR4.FRED
#UD for SYS{EXIT,RET}, SWAPGS, {CLR,SET}SSBSY – changes to STAR, FMASK, GSBASE, PL0_SSP MSRs
|
| 16 |
reserved |
| 15 |
reserved |
| 14 |
reserved |
| 13 |
reserved |
| 12 (FAST_REP_CMPSB...) |
fast short REP CMPSB/SCASB |
| 11 (FAST_REP_STOSB) |
fast short REP STOSB |
| 10 (FAST_REP_MOVSB) |
fast zero-length REP MOVSB |
| 9 (DEDUP) |
DEDUP |
| 8 (ARCH_PERFMON) |
standard leaf 0000_0023h |
| 7 (CMPCCXADD) |
CMPccXADD |
| 6 (LASS) |
LASS |
| 5 (AVX512BF16) |
AVX512BF16 |
| 4 (AVX_VNNI) |
AVX_VNNI |
| 3 (RAO_INT) |
RAO_INT |
| 2 (SM4) |
SM4 |
| 1 (SM3) |
SM3 |
| 0 (SHA512) |
SHA512 |
| EBX |
bits |
description |
| 31...4 |
reserved |
| 3 (NO_LCMV) |
MISC_ENABLE.LCMV no longer supported |
| 2 |
reserved |
| 1 (PBNDKB) |
PBNDKB, TSE_CAPABILITY MSR |
| 0 (PPIN) |
Per Processor Inventory Number – PPIN and PPIN_CTL MSRs |
| ECX |
bits |
description |
| 31...6 |
reserved |
| 5 (MSR_IMM) |
MSR_IMM |
| 4 (SIPI64) |
SIPI64 |
| 3 |
reserved |
| 2 (X86S) |
x86-S |
| 1 (RDT_A_ASYM) |
asymmetric RDT-A QoS allocation, standard leaf 0000_0028h |
| 0 (RDT_M_ASYM) |
asymmetric RDT-M QoS monitoring, standard leaf 0000_0027h |
| EDX |
bits |
description |
| 31 |
reserved |
| 30 |
reserved |
| 29 |
reserved |
| 28 |
reserved |
| 27 |
reserved |
| 26 |
reserved |
| 25 |
reserved |
| 24 (SLSM) |
static lock step mode, INTEGRITY_STATUS MSR with LOCKSTEP bit |
| 23 (MWAIT) |
MWAIT ok even if standard leaf 0000_0001h ECX bit 3 (MONITOR) = 0 |
| 22 (SEC_TEE_ATT) |
can use S3M for SGX attestation |
| 21 (APX_F) |
APX_F, standard leaf 0000_0029h |
| 20 |
reserved |
| 19 (AVX10) |
AVX10, standard leaf 0000_0024h |
| 18 (CET_SSS) |
CET supervisor shadow stacks |
| 17 (UIRET_UIF) |
UIRET_UIF |
| 16 |
reserved |
| 15 (USER_MSR) |
URDMSR/UWRMSR |
| 14 (PREFETCHI) |
PREFETCHIT0/PREFETCHIT1 |
| 13 (UTMR) |
UTMR, UINTR_TIMER MSR |
| 12 |
reserved |
| 11 |
reserved |
| 10 (AVX_VNNI_INT16) |
AVX_VNNI_INT16 |
| 9 |
reserved |
| 8 (AMX_COMPLEX) |
AMX_COMPLEX |
| 7 |
reserved |
| 6 |
reserved |
| 5 (AVX_NE_CONV.) |
AVX_NE_CONVERT |
| 4 (AVX_VNNI_INT8) |
AVX_VNNI_INT8 |
| 3 |
reserved |
| 2 |
reserved |
| 1 |
reserved |
| 0 |
reserved |
|
output
(sub 2) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...8 |
reserved |
| 7 (MON_MITG_NO) |
not affected by MONITOR/UMONITOR performance or power issues
due to the instructions exceeding an internal tracking table's capacity |
| 6 (UC_LOCK_DIS) |
#AC(4) if MEMORY_CTRL.UC_LK_DIS_XX_EN = 1
(legacy implementation: #GP(0) if CORE_CAPABILITIES.UC_LK_DIS_GP_avl = 1) |
| 5 (MCDT_NO) |
not affected by MCDT (aka MXCSR Configuration Dependent Timing) |
| 4 (BHI_CTRL) |
SPEC_CTRL.BHI_DIS_S, IBHF |
| 3 (DDP_CTRL) |
SPEC_CTRL.DDP_DIS_U |
| 2 (RRSBA_CTRL) |
SPEC_CTRL.RRSBA_DIS_U
SPEC_CTRL.RRSBA_DIS_S |
| 1 (IPRED_CTRL) |
SPEC_CTRL.IPRED_DIS_U
SPEC_CTRL.IPRED_DIS_S |
| 0 (PSFD) |
SPEC_CTRL.PSF_DIS |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0009h
|
|
| input |
EAX=0000_0009h |
get DCA parameters #1 |
|
| output |
EAX |
bits |
description |
| 31...0 |
value of PLATFORM_DCA_CAP MSR (0000_01F8h, bits 31...0) |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_000Ah
|
|
| input |
EAX=0000_000Ah |
get architectural perf mon information #1 |
|
| output |
EAX |
bits |
description |
| 31...24 |
length of EBX bit vector |
| 23...16 |
bit width of perf mon counter(s) |
| 15...8 |
number of perf mon counters per logical processor |
| 7...0 |
revision |
| EBX |
bits |
description |
| 31...13 |
reserved |
| 12 |
LBR inserts unavailable |
| 11 |
topdown retiring unavailable |
| 10 |
topdown frontend bound unavailable |
| 9 |
topdown bad speculation unavailable |
| 8 |
topdown backend bound unavailable |
| 7 |
topdown slots event unavailable |
| 6 |
branch mispredicts retired event unavailable |
| 5 |
branch instructions retired event unavailable |
| 4 |
last level cache misses event unavailable |
| 3 |
last level cache references event unavailable |
| 2 |
reference cycles event unavailable |
| 1 |
instructions retired event unavailable |
| 0 |
core cycles event unavailable |
| ECX |
bits |
description |
| 31...0 |
fixed counters bit mask |
| EDX |
bits |
description |
| 31...20 |
reserved |
| 19...16 |
number of topdown microarchitecture analysis (TMA) slots per cycle |
| 15 |
any thread mode deprecation |
| 14...13 |
reserved |
| 12...5 |
bit width of fixed-function perf mon counters (if revision > 1) |
| 4...0 |
number of fixed-function perf mon counters (if revision > 1) |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_000Bh
|
|
| input |
EAX=0000_000Bh |
get topology enumeration information #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n until EBX[15...0] = 0) |
|
output
(sub n) |
EAX |
bits |
description |
| 31...5 |
reserved |
| 4...0 |
number of bits that x2APIC ID must be shifted to right for next domain |
| EBX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
number of logical processors across all the instances of this domain |
| ECX |
bits |
description |
| 31...16 |
reserved |
| 15...8 |
domain type
(0=invalid, 1=thread, 2=core, implied=package/socket, 3-255=reserved) |
| 7...0 |
input ECX sub-leaf index |
| EDX |
bits |
description |
| 31...0 |
x2APIC ID – always valid – does not vary with sub-leaf index |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_000Dh
|
|
| input |
EAX=0000_000Dh |
get extended state enumeration #1 |
| ECX=0000_00xxh |
sub-leaf to query (0=main, 1=reserved, 2...62 as per XCR0.n) |
|
output
(main) |
EAX |
bits |
description |
| 31...0 |
valid XCR0.31...0 bits |
| EBX |
bits |
description |
| 31...0 |
current size (in bytes) of XSAVE/XRSTOR area (as per current XCR0) |
| ECX |
bits |
description |
| 31...0 |
max. size (in bytes) of XSAVE/XRSTOR area (incl. XSAVE.HEADER) |
| EDX |
bits |
description |
| 31...0 |
valid XCR0.63...32 bits |
|
output
(res.) |
EAX |
bits |
description |
| 31...5 |
reserved |
| 4 |
XFD and XFD_ERR |
| 3 |
XSAVES/XRSTORS and XSS |
| 2 |
XGETBV with ECX=1 |
| 1 |
XSAVEC and compacted form of XRSTOR |
| 0 |
XSAVEOPT |
| EBX |
bits |
description |
| 31...0 |
size (in bytes) in XSAVE area for XCR0 | XSS |
| ECX |
bits |
description |
| 31...0 |
valid XSS.31...0 bits |
| EDX |
bits |
description |
| 31...0 |
valid XSS.63...32 bits |
|
output
(sub) |
EAX |
bits |
description |
| 31...0 |
size (in bytes) in XSAVE/XRSTOR area for XCR0.n (n=ECX=2...62)
0 if n was invalid
|
| EBX |
bits |
description |
| 31...0 |
offset (in bytes) in XSAVE/XRSTOR area for XCR0.n (n=ECX=2...62)
0 if n was invalid
|
| ECX |
bits |
description |
| 31...3 |
reserved |
| 2 |
XFD.n and XFD_ERR.n (n=ECX=2...62) are supported for component |
| 1 |
0 if component immediately follows previous component
1 if component is aligned to next 64 byte boundary
|
| 0 |
1 if n was valid in XSS
0 if n was invalid
|
| EDX |
bits |
description |
| 31...0 |
reserved
0 if n was invalid
|
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_000Fh
|
|
| input |
EAX=0000_000Fh |
get RDT-M (QoS monitoring) enumeration #1 |
| ECX=0000_00xxh |
sub-leaf to query (0=resources, 1...n as per EDX reported by sub-leaf 0) |
|
output
(main) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31...0 |
max. range (zero-based) of RMID within this phys. processor of all types |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...2 |
reserved |
| 1 |
L3 cache QoS monitoring |
| 0 |
reserved |
|
output
(1=L3) |
EAX |
bits |
description |
| 31...11 |
reserved |
| 10 |
non-CPU agent present, supporting Intel RDT MBM |
| 9 |
non-CPU agent present, supporting Intel RDT CMT |
| 8 |
counter bit 61 is overflow bit |
| 7...0 |
counter width, offset from 24 bits (if 0, use FMS to pick the width) |
| EBX |
bits |
description |
| 31...0 |
conversion factor from QM_CTR value to occupancy metric (bytes) |
| ECX |
bits |
description |
| 31...0 |
max. range (zero-based) of RMID within this resource type |
| EDX |
bits |
description |
| 31...3 |
reserved |
| 2 |
L3 local external bandwidth monitoring |
| 1 |
L3 total external bandwidth monitoring |
| 0 |
L3 occupancy monitoring |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0010h
|
|
| input |
EAX=0000_0010h |
get RDT-A (QoS allocation) enumeration #1 |
| ECX=0000_00xxh |
sub-leaf to query (0=resources, 1...n as per EBX reported by sub-leaf 0) |
|
output
(main) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31...7 |
reserved |
| 6 |
RP – resource priority |
| 5 |
CBA – cache bandwidth allocation |
| 4 |
reserved |
| 3 |
MBA – memory bandwidth allocation |
| 2 |
L2 cache QoS enforcement |
| 1 |
L3 cache QoS enforcement |
| 0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...2 |
reserved |
| 1 |
AMD: L3 cache allocation enforcement support |
| 0 |
reserved |
|
output
(1=L3) |
EAX |
bits |
description |
| 31...5 |
reserved |
| 4...0 |
length of capacity bit mask for resource n using minus-one notation |
| EBX |
bits |
description |
| 31...0 |
bit-granular map of isolation/contention of allocation units |
| ECX |
bits |
description |
| 31...4 |
reserved |
| 3 |
non-contiguous capacity bitmasks |
| 2 |
code/data prioritization – set L3_QOS_CFG MSR bit 0 to 1 to enable |
| 1 |
(ISE 049) was: updates of COS should be infrequent
(ISE 050) now: non-CPU agent present, supporting Intel RDT L3 CAT |
| 0 |
reserved |
| EDX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
highest COS number supported for resource n |
|
output
(2=L2) |
EAX |
bits |
description |
| 31...5 |
reserved |
| 4...0 |
length of capacity bit mask for resource n using minus-one notation |
| EBX |
bits |
description |
| 31...0 |
bit-granular map of isolation/contention of allocation units |
| ECX |
bits |
description |
| 31...4 |
reserved |
| 3 |
non-contiguous capacity bitmasks |
| 2 |
code/data prioritization – set L2_QOS_CFG MSR bit 0 to 1 to enable |
| 1...0 |
reserved |
| EDX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
highest COS number supported for resource n |
|
output
(3=MBA) |
EAX |
bits |
description |
| 31...12 |
reserved |
| 11...0 |
maximum MBA throttling value for resource n using minus-one notation |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...3 |
reserved |
| 2 |
response to delay value is linear |
| 1 |
reserved |
| 0 |
per thread MBA controls |
| EDX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
highest COS number supported for resource n |
|
output
(5=CBA) |
EAX |
bits |
description |
| 31...12 |
reserved |
| 11...8 |
scope of CBA QoS_Core_BW_Thrtl_n MSRs is logical processor |
| 7...0 |
maximum CBA throttling value for resource n using minus-one notation |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...4 |
reserved |
| 3 |
approximately linear response |
| 2...0 |
reserved |
| EDX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
highest COS number supported for resource n |
|
output
(6=RP) |
EAX |
bits |
description |
| 31...2 |
reserved |
| 1 |
package enable via RESOURCE_PRIORITY_PKG MSR |
| 0 |
thread enable via RESOURCE_PRIORITY MSR |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0012h
|
|
| input |
EAX=0000_0012h |
get SGX resource enumeration #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0=capabilities, 1=SECS, 2...n=EPC) |
|
output
(capab.) |
EAX |
bits |
description |
| 31...13 |
reserved |
| 12 |
ENCLU[EGETKEY256] and ENCLU[EREPORT2], and
SGXLEPUBKEYHASH[4,5] and SGXLECONFIG MSRs |
| 11 |
ENCLU[EDECCSSA] |
| 10 |
ENCLS[EUPDATESVN] |
| 9...8 |
reserved |
| 7 |
ENCLU[EVERIFYREPORT2] |
| 6 |
ETRACKC/ERDINFO/ELDBC/ELDUC |
| 5 |
ENCLV and EINCVIRTCHILD/EDECVIRTCHILD/ESETCONTEXT |
| 4...2 |
reserved |
| 1 (SGX2) |
EAUG/EMODPR/EMODT and EACCEPT/EMODPE/EACCEPTCOPY |
| 0 (SGX1) |
ENCLS and ENCLU, #PF.SGX |
| EBX |
bits |
description |
| 31...0 |
bit vector of supported extended features (that can be written to SSA.MISC) |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...16 |
reserved |
| 15...8 |
maximum enclave size in 2^n bytes when in PM64 |
| 7...0 |
maximum enclave size in 2^n bytes when not in PM64 |
|
output
(SECS) |
EAX |
bits |
description |
| 31...0 |
SECS.ATTRIBUTES.31...0 that can be set with ENCLS[ECREATE] |
| EBX |
bits |
description |
| 31...0 |
SECS.ATTRIBUTES.63...32 that can be set with ENCLS[ECREATE] |
| ECX |
bits |
description |
| 31...0 |
SECS.ATTRIBUTES.95...64 that can be set with ENCLS[ECREATE] |
| EDX |
bits |
description |
| 31...0 |
SECS.ATTRIBUTES.127...96 that can be set with ENCLS[ECREATE] |
|
output
(EPC) |
EAX |
bits |
description |
| 31...12 |
EPC base bits 31...12 |
| 11...4 |
reserved |
| 3...0 |
0000b = not valid, 0001b = leaf is valid, other = reserved |
| EBX |
bits |
description |
| 31...20 |
reserved |
| 19...0 |
EPC base bits 51...32 |
| ECX |
bits |
description |
| 31...12 |
EPC size bits 31...12 |
| 11...4 |
reserved |
| 3...0 |
EPC section protection
0000b = not valid
0001b = confidentiality + integrity + replay
0010b = confidentiality
0011b = confidentiality + integrity
other = reserved
|
| EDX |
bits |
description |
| 31...20 |
reserved |
| 19...0 |
EPC size bits 51...32 |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0014h
|
|
| input |
EAX=0000_0014h |
get processor trace (PT) capability enumeration #1 |
| ECX=0000_00xxh |
sub-leaf to query (0=capabilities, 1=details – 1...31 as per EAX reported by sub-leaf 0) |
|
output
(capab.) |
EAX |
bits |
description |
| 31...0 |
max sub-leaf |
| EBX |
bits |
description |
| 31...10 |
reserved |
| 9 (PTTT) |
PT trigger tracing |
| 8 (TNT_DIS) |
TNT packet generation disabling, RTIT_CTL.DisTNT |
| 7 (EVENT_TRACE) |
event trace packet generation, RTIT_CTL.EventEn |
| 6 (PMI_PRESERVE) |
PSB and PMI preservation |
| 5 (PWR_EVT_TRACE) |
power event trace, RTIT_CTL.PwrEvtEn |
| 4 (PTWRITE) |
PTWRITE, RTIT_CTL.PTWEn, RTIT_CTL.FUPonPTW |
| 3 (MTC) |
MTC timing packet, suppression of COFI-based packets |
| 2 (IP_FILTER) |
IP filtering, TraceStop filtering, PT MSR preservation across warm reset |
| 1 (CYC_ACC) |
configurable PSB, cycle-accurate mode |
| 0 (CR3_FILTER) |
CR3 filtering, RTIT_CTL.CR3Filter, RTIT_CR3_MATCH |
| ECX |
bits |
description |
| 31 (LIP) |
IP payloads are LIP |
| 30...4 |
reserved |
| 3 (TRACE_TR._SUBS.) |
output to trace transport subsystem |
| 2 (SNGL_RNG_OUT) |
single-range output scheme |
| 1 (MENTRY) |
ToPA tables allow multiple output entries |
| 0 (TOPAOUT) |
ToPA output |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(details) |
EAX |
bits |
description |
| 31...16 |
bitmap of supported MTC period encodings |
| 15...11 |
reserved |
| 10...8 |
number of RTIT_TRIGGERx_CFG MSRs (triggers = 4x this value) |
| 7...3 |
reserved |
| 2...0 |
number of configurable address ranges for filtering |
| EBX |
bits |
description |
| 31...16 |
bitmap of supported configurable PSB frequency encodings |
| 15...0 |
bitmap of supported cycle threshold value encodings |
| ECX |
bits |
description |
| 31...16 |
reserved |
| 15 |
trigger input DR match supported |
| 14...2 |
reserved |
| 1 |
trigger actions TRACE_PAUSE and TRACE_RESUME supported |
| 0 |
trigger action EN_ICNT supported |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0015h
|
|
| input |
EAX=0000_0015h |
get processor frequency information #1 |
|
| output |
EAX |
bits |
description |
| 31...0 |
denominator (TSC frequency = core crystal clock frequency * EBX/EAX) |
| EBX |
bits |
description |
| 31...0 |
numerator (TSC frequency = core crystal clock frequency * EBX/EAX) |
| ECX |
bits |
description |
| 31...0 |
core crystal clock frequency in Hz |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0016h
|
|
| input |
EAX=0000_0016h |
get processor frequency information #1 |
|
| output |
EAX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
core base frequency in MHz |
| EBX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
core maximum frequency in MHz |
| ECX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
bus (reference) frequency in MHz |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0017h
|
|
| input |
EAX=0000_0017h |
get processor vendor attribute information #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n as per EAX reported by sub-leaf 0) |
|
output
(main) |
EAX |
bits |
description |
| 31...0 |
max sub-leaf |
| EBX |
bits |
description |
| 31...17 |
reserved |
| 16 |
vendor ID uses industry standard enumeration scheme (0=no, 1=yes) |
| 15...0 |
vendor ID (1=Spreadtrum) |
| ECX |
bits |
description |
| 31...0 |
project ID |
| EDX |
bits |
description |
| 31...0 |
stepping ID |
|
output
(1 of 3) |
EAX |
bits |
description |
| 31...0 |
UTF-8 encoded vendor brand string – part 1/12 |
| EBX |
bits |
description |
| 31...0 |
UTF-8 encoded vendor brand string – part 2/12 |
| ECX |
bits |
description |
| 31...0 |
UTF-8 encoded vendor brand string – part 3/12 |
| EDX |
bits |
description |
| 31...0 |
UTF-8 encoded vendor brand string – part 4/12 |
|
output
(2 of 3) |
EAX |
bits |
description |
| 31...0 |
UTF-8 encoded vendor brand string – part 5/12 |
| EBX |
bits |
description |
| 31...0 |
UTF-8 encoded vendor brand string – part 6/12 |
| ECX |
bits |
description |
| 31...0 |
UTF-8 encoded vendor brand string – part 7/12 |
| EDX |
bits |
description |
| 31...0 |
UTF-8 encoded vendor brand string – part 8/12 |
|
output
(3 of 3) |
EAX |
bits |
description |
| 31...0 |
UTF-8 encoded vendor brand string – part 9/12 |
| EBX |
bits |
description |
| 31...0 |
UTF-8 encoded vendor brand string – part 10/12 |
| ECX |
bits |
description |
| 31...0 |
UTF-8 encoded vendor brand string – part 11/12 |
| EDX |
bits |
description |
| 31...0 |
UTF-8 encoded vendor brand string – part 12/12 |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0018h
|
|
| input |
EAX=0000_0018h |
get TLB information #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n as per EAX reported by sub-leaf 0) |
|
output
(main) |
EAX |
bits |
description |
| 31...0 |
max sub-leaf |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...5 |
reserved |
| 4...0 |
TC type (always 00000b=invalid) |
|
output
(sub) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31...16 |
ways |
| 15...11 |
reserved |
| 10...8 |
partitioning (0: soft between logical processors sharing this TC) |
| 7...4 |
reserved |
| 3 |
1G |
| 2 |
4M |
| 1 |
2M |
| 0 |
4K |
| ECX |
bits |
description |
| 31...0 |
sets |
| EDX |
bits |
description |
| 31...26 |
reserved |
| 25...14 |
max. number of addressable IDs for logical processors sharing this TC - 1 |
| 13...9 |
reserved |
| 8 |
fully associative? |
| 7...5 |
TC level (starts at 1) |
| 4...0 |
TC type (00000b=invalid, 00001b=data, 00010b=code, 00011b=unified,
00100b=load-only [ld hits, ld/st fills], 00101b=store-only [st hits, st fills])
(note: unified may either support entries shared by code and data, or utilize separate entries for code versus data)
|
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0019h
|
|
| input |
EAX=0000_0019h |
get KL information #1 |
|
| output |
EAX |
bits |
description |
| 31...3 |
reserved |
| 2 (NO_DEC) |
KL restricted to no-decrypt |
| 1 (NO_ENC) |
KL restricted to no-encrypt |
| 0 (CPL0) |
KL restricted to CPL0 |
| EBX |
bits |
description |
| 31...5 |
reserved |
| 4 (IWKEYBACKUP) |
internal wrapping key backup supported
COPY_LOCAL_TO_PLATFORM.IW_Key_Backup MSR D91h bit 0 (WO)
COPY_PLATFORM_TO_LOCAL.IW_Key_Backup MSR D92h bit 0 (WO)
COPY_STATUS.IW_Key_Copy_Successful MSR 990h bit 0 (RO)
IWKEYBACKUP_STATUS.Backup_Restore_Valid MSR 991h bit 0 (RO)
IWKEYBACKUP_STATUS.Storage_Rd_Wr_Error MSR 991h bit 2 (RO)
IWKEYBACKUP_STATUS.IW_Key_Backup_Consumed MSR 991h bit 3 (RO)
|
| 3 |
reserved |
| 2 (AES_WIDE) |
AES KL wide instructions supported |
| 1 |
reserved |
| 0 (AES_KL_E) |
AES KL enabled (CR4.KL=1) – note: a SKU may force 0 when in SMM |
| ECX |
bits |
description |
| 31...2 |
reserved |
| 1 (RAND_IW_KEY) |
supports KeySource=1, i.e. randomization of the internal wrapping key |
| 0 (NO_BACKUP) |
LOADIWKEY supports NoBackup parameter |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_001Ah
|
|
| input |
EAX=0000_001Ah |
get core model information #1 |
|
| output |
EAX |
bits |
description |
| 31...24 |
core type (10h=reserved, 20h=Atom, 30h=reserved, 40h=Core) |
| 23...0 |
core native model ID |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_001Bh
|
|
| input |
EAX=0000_001Bh |
get PCONFIG information #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0=invalid, 1=target ID, 2...n=invalid – see EAX bits 11...0 in output) |
|
output
(invalid) |
EAX |
bits |
description |
| 31...12 |
reserved |
| 11...0 |
sub-leaf (0) – invalid |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(target ID) |
EAX |
bits |
description |
| 31...12 |
reserved |
| 11...0 |
sub-leaf (1) – target ID |
| EBX |
bits |
description |
| 31...0 |
target ID 1 – (0=invalid, 1=MK-TME, 2=TSE, 3...n=reserved) |
| ECX |
bits |
description |
| 31...0 |
target ID 2 – (0=invalid, 1=MK-TME, 2=TSE, 3...n=reserved) |
| EDX |
bits |
description |
| 31...0 |
target ID 3 – (0=invalid, 1=MK-TME, 2=TSE, 3...n=reserved) |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_001Ch
|
|
| input |
EAX=0000_001Ch |
get LBR information #1 |
|
| output |
EAX |
bits |
description |
| 31 |
LBR IP value type (0=EIP, 1=LIP) – note: LIP=EIP if flat memory model |
| 30 |
LBR cleared on MWAIT > C1 |
| 29...8 |
reserved |
| 7...0 |
for each bit n = 1, LBR_DEPTH.DEPTH value 8*(n+1) is supported |
| EBX |
bits |
description |
| 31...3 |
reserved |
| 2 |
LBR_CTL[3] for call stack mode |
| 1 |
LBR_CTL[22...16] for branch filtering |
| 0 |
LBR_CTL[2...1] for CPL filtering |
| ECX |
bits |
description |
| 31...20 |
reserved |
| 19...16 |
event logging bitmap – bit per perf mon counter with LBR event logging |
| 15...3 |
reserved |
| 2 |
LBR_x_INFO[59...56] indicates branch type |
| 1 |
LBR_x_INFO[15...0] indicates cycles since last LBR entry
LBR_x_INFO[60] indicates whether cycle count is valid |
| 0 |
LBR_x_INFO[63] indicates branch misprediction |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_001Dh
|
|
| input |
EAX=0000_001Dh |
get AMX tile information #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n as per EAX reported by sub-leaf 0) |
|
output
(main) |
EAX |
bits |
description |
| 31...0 |
max sub-leaf |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(palette 1) |
EAX |
bits |
description |
| 31...16 |
bytes per tile (1024) |
| 15...0 |
total tile bytes (8192) |
| EBX |
bits |
description |
| 31...16 |
max names (8) – number of tile registers |
| 15...0 |
bytes per row (64) |
| ECX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
max rows (16) |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_001Eh
|
|
| input |
EAX=0000_001Eh |
get AMX TMUL information #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n as per EAX reported by sub-leaf 0) |
|
output
(sub 0) |
EAX |
bits |
description |
| 31...0 |
max sub-leaf |
| EBX |
bits |
description |
| 31...24 |
reserved |
| 23...8 |
TMUL max N (64) – column bytes |
| 7...0 |
TMUL max K (16) – rows or columns |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(sub 1) |
EAX |
bits |
description |
| 31...9 |
reserved |
| 8 |
AMX-MOVRS |
| 7 |
AMX-AVX512 |
| 6 |
AMX-TF32 (FP19) |
| 5 |
AMX-TRANSPOSE |
| 4 |
AMX-FP8 |
| 3 |
AMX-FP16 |
| 2 |
AMX-COMPLEX |
| 1 |
AMX-BF16 |
| 0 |
AMX-INT8 |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_001Fh
|
|
| input |
EAX=0000_001Fh |
get topology enumeration information #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n until EBX[15...0] = 0) |
|
output
(sub n) |
EAX |
bits |
description |
| 31...5 |
reserved |
| 4...0 |
number of bits that x2APIC ID must be shifted to right for next domain |
| EBX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
number of logical processors across all the instances of this domain |
| ECX |
bits |
description |
| 31...16 |
reserved |
| 15...8 |
domain type
(0=invalid, 1=thread, 2=core, 3=module, 4=tile, 5=die, 6=die group, implied=package/socket, 7-255=reserved) |
| 7...0 |
input ECX sub-leaf index |
| EDX |
bits |
description |
| 31...0 |
x2APIC ID – always valid – does not vary with sub-leaf index |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0020h
|
|
| input |
EAX=0000_0020h |
get HRESET information #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n as per EAX reported by sub-leaf 0) |
|
output
(sub 0) |
EAX |
bits |
description |
| 31...0 |
max sub-leaf |
| EBX |
bits |
description |
| 31...1 |
reserved |
| 0 |
HRESET EAX[0], HRESET_ENABLE[0] |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0021h
|
|
| input |
EAX=0000_0021h |
get TDX software information #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n as per EAX reported by sub-leaf 0) |
|
output
(capab.) |
EAX |
bits |
description |
| 31...0 |
max sub-leaf |
| EBX |
bits |
description |
| 31...0 |
65746E49h ("Inte") |
| ECX |
bits |
description |
| 31...0 |
20202020h (" ") |
| EDX |
bits |
description |
| 31...0 |
5844546Ch ("lTDX") |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0023h
|
|
| input |
EAX=0000_0023h |
get architectural perf mon extended information #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n as per EAX reported by sub-leaf 0) |
|
output
(sub 0) |
EAX |
bits |
description |
| 31...0 |
sub-leaf bitmask |
| EBX |
bits |
description |
| 31...3 |
reserved |
| 2 |
PERFEVTSELn.RDPMC_USR_DISABLE supported |
| 1 |
PERFEVTSELn.EqualFlag supported |
| 0 |
PERFEVTSELn.UnitMask2 supported |
| ECX |
bits |
description |
| 31...8 |
reserved |
| 7...0 |
top-down microarchitecture analysis (TMA) slots per cycle |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(sub 1) |
EAX |
bits |
description |
| 31...0 |
counter bitmask – general purpose |
| EBX |
bits |
description |
| 31...0 |
counter bitmask – fixed function |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(sub 2) |
EAX |
bits |
description |
| 31...0 |
auto counter reload (ACR) "can reload" bitmask – general purpose |
| EBX |
bits |
description |
| 31...0 |
auto counter reload (ACR) "can reload" bitmask – fixed function |
| ECX |
bits |
description |
| 31...0 |
auto counter reload (ACR) "can trigger" bitmask – general purpose |
| EDX |
bits |
description |
| 31...0 |
auto counter reload (ACR) "can trigger" bitmask – fixed function |
|
output
(sub 3) |
EAX |
bits |
description |
| 31...13 |
reserved |
| 12 |
LBR inserts |
| 11 |
topdown retiring |
| 10 |
topdown frontend bound |
| 9 |
topdown bad speculation |
| 8 |
topdown backend bound |
| 7 |
topdown slots |
| 6 |
branch mispredicts retired |
| 5 |
branch instructions retired |
| 4 |
last level cache misses |
| 3 |
last level cache references |
| 2 |
reference cycles |
| 1 |
instructions retired |
| 0 |
core cycles |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(sub 4) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31 |
reserved |
| 30 |
counter group – AUX |
| 29 |
counter group – GPR |
| 28...24 |
reserved |
| 23...17 |
counter group – XER (55:49) |
| 16...10 |
reserved |
| 9...8 |
counter group – LBR (41:40) |
| 7 |
reserved |
| 6 |
counters sub-group – performance metrics |
| 5 |
counters sub-group – fixed function |
| 4 |
counters sub-group – general purpose |
| 3 |
PMC_GPn_CFG_C.ALLOW_IN_RECORD
PMC_FXm_CFG_C.ALLOW_IN_RECORD |
| 2...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(sub 5) |
EAX |
bits |
description |
| 31...0 |
PEBS counter bitmask – general purpose |
| EBX |
bits |
description |
| 31...0 |
PEBS counter PDIST bitmask – general purpose |
| ECX |
bits |
description |
| 31...0 |
PEBS counter bitmask – fixed function |
| EDX |
bits |
description |
| 31...0 |
PEBS counter PDIST bitmask – fixed function |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0024h
|
|
| input |
EAX=0000_0024h |
get AVX10 information #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n as per EAX reported by sub-leaf 0) |
|
output
(sub 0) |
EAX |
bits |
description |
| 31...0 |
max sub-leaf |
| EBX |
bits |
description |
| 31...19 |
reserved |
| 18 |
VL512 |
| 17 |
VL256 |
| 16 |
VL128 |
| 15...8 |
reserved |
| 7...0 |
AVX10 version |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(sub 1) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...3 |
reserved |
| 2 |
AVX10_V1_AUX (was AVX10_VNNI_INT) |
| 1 |
reserved |
| 0 |
VPMM |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0027h
|
|
| input |
EAX=0000_0027h |
get asymmetric RDT-M (QoS monitoring) enumeration #1 |
| ECX=0000_00xxh |
sub-leaf to query (0=resources, 1...n as per EDX reported by sub-leaf 0) |
|
output
(main) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31...0 |
max. range (zero-based) of RMID within this phys. processor of all types |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...2 |
reserved |
| 1 |
L3 cache QoS monitoring |
| 0 |
reserved |
|
output
(1=L3) |
EAX |
bits |
description |
| 31...11 |
reserved |
| 10 |
non-CPU agent present, supporting Intel RDT MBM |
| 9 |
non-CPU agent present, supporting Intel RDT CMT |
| 8 |
counter bit 61 is overflow bit |
| 7...0 |
counter width, offset from 24 bits (if 0, use FMS to pick the width) |
| EBX |
bits |
description |
| 31...0 |
conversion factor from QM_CTR value to occupancy metric (bytes) |
| ECX |
bits |
description |
| 31...0 |
max. range (zero-based) of RMID within this resource type |
| EDX |
bits |
description |
| 31...3 |
reserved |
| 2 |
L3 local external bandwidth monitoring |
| 1 |
L3 total external bandwidth monitoring |
| 0 |
L3 occupancy monitoring |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0028h
|
|
| input |
EAX=0000_0028h |
get asymmetric RDT-A (QoS allocation) enumeration #1 |
| ECX=0000_00xxh |
sub-leaf to query (0=resources, 1...n as per EBX reported by sub-leaf 0) |
|
output
(main) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31...7 |
reserved |
| 6 |
RP – resource priority |
| 5 |
CBA – cache bandwidth allocation |
| 4 |
reserved |
| 3 |
MBA – memory bandwidth allocation |
| 2 |
L2 cache QoS enforcement |
| 1 |
L3 cache QoS enforcement |
| 0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(1=L3) |
EAX |
bits |
description |
| 31...5 |
reserved |
| 4...0 |
length of capacity bit mask for resource n using minus-one notation |
| EBX |
bits |
description |
| 31...0 |
bit-granular map of isolation/contention of allocation units |
| ECX |
bits |
description |
| 31...4 |
reserved |
| 3 |
non-contiguous capacity bitmasks |
| 2 |
code/data prioritization – set L3_QOS_CFG MSR bit 0 to 1 to enable |
| 1 |
(ISE 049) was: updates of COS should be infrequent
(ISE 050) now: non-CPU agent present, supporting Intel RDT L3 CAT |
| 0 |
reserved |
| EDX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
highest COS number supported for resource n |
|
output
(2=L2) |
EAX |
bits |
description |
| 31...5 |
reserved |
| 4...0 |
length of capacity bit mask for resource n using minus-one notation |
| EBX |
bits |
description |
| 31...0 |
bit-granular map of isolation/contention of allocation units |
| ECX |
bits |
description |
| 31...4 |
reserved |
| 3 |
non-contiguous capacity bitmasks |
| 2 |
code/data prioritization – set L2_QOS_CFG MSR bit 0 to 1 to enable |
| 1...0 |
reserved |
| EDX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
highest COS number supported for resource n |
|
output
(3=MBA) |
EAX |
bits |
description |
| 31...12 |
reserved |
| 11...0 |
maximum MBA throttling value for resource n using minus-one notation |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...3 |
reserved |
| 2 |
response to delay value is linear |
| 1 |
reserved |
| 0 |
per thread MBA controls |
| EDX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
highest COS number supported for resource n |
|
output
(5=CBA) |
EAX |
bits |
description |
| 31...12 |
reserved |
| 11...8 |
scope of CBA QoS_Core_BW_Thrtl_n MSRs is logical processor |
| 7...0 |
maximum CBA throttling value for resource n using minus-one notation |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...4 |
reserved |
| 3 |
approximately linear response |
| 2...0 |
reserved |
| EDX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
highest COS number supported for resource n |
output
(6=RP) |
EAX |
bits |
description |
| 31...2 |
reserved |
| 1 |
package enable via RESOURCE_PRIORITY_PKG MSR |
| 0 |
thread enable via RESOURCE_PRIORITY MSR |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
standard leaf 0000_0029h
|
|
| input |
EAX=0000_0029h |
get APX information #1 |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n as per EAX reported by sub-leaf 0) |
|
output
(sub 0) |
EAX |
bits |
description |
| 31...0 |
max sub-leaf |
| EBX |
bits |
description |
| 31...1 |
reserved |
| 0 |
APX_NCI_NDD_NF |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug. (note: deprecated if NO_LCMV = 1) |
Intel Xeon Phi leaf 2000_0000h
|
|
| input |
EAX=2000_0000h |
get maximum supported leaf |
|
| output |
EAX=xxxx_xxxxh |
maximum supported leaf |
Intel Xeon Phi leaf 2000_0001h
|
|
| input |
EAX=2000_0001h |
get processor information |
|
| output |
EDX=xxxx_xxxxh |
feature flags |
description of indicated feature |
| 31...5 |
reserved |
| 4 (K1OM) |
MVEX (62h), ZMM0...31, K0...7, transform modifiers, VSIB512, disp8*N |
| 3 (L1OM_62_EN) |
L1OM opcode map 62h enabled |
| 2 (L1OM_D6_EN) |
L1OM opcode map D6h enabled |
| 1 (L1OM) |
L1OM (62h/D6h), V0...31, K0...7, transform modifiers, VSIB512, disp8*N |
| 0 |
reserved |
hypervisor leaf 4000_0000h
|
|
| input |
EAX=4000_0000h |
get hypervisor information – vendor #1 |
|
| output |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX-ECX-EDX |
bits |
description |
| Microsoft Hv |
Microsoft |
| VMwareVMware |
VMware |
| prl hyperv |
Parallels |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the hypervisor. |
hypervisor leaf 4000_0001h
|
|
| input |
EAX=4000_0001h |
get hypervisor information – interface #1 |
|
| output |
EAX |
bits |
description |
| 31...0 |
interface signature (e.g. 31237648h = "Hv#1") |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the hypervisor. |
hypervisor leaf 4000_0002h
|
|
| input |
EAX=4000_0002h |
get hypervisor information – version #1 |
|
| output |
EAX |
bits |
description |
| 31...0 |
build number |
| EBX |
bits |
description |
| 31...16 |
major version |
| 15...0 |
minor version |
| ECX |
bits |
description |
| 31...0 |
service pack |
| EDX |
bits |
description |
| 31...24 |
service branch |
| 23...0 |
service number |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the hypervisor. |
hypervisor leaf 4000_0003h
|
|
| input |
EAX=4000_0003h |
get hypervisor information – features #1 |
|
| output |
EAX |
bits |
description of features based on current privileges (=virtual MSRs) |
| 31...14 |
reserved |
| 13 |
reenlightenment control |
| 12 |
debug MSRs |
| 11 |
timer frequency MSRs |
| 10 |
virtual guest idle state MSR |
| 9 |
partition reference TSC MSR |
| 8 |
access statistics pages MSRs |
| 7 |
virtual system reset MSR |
| 6 |
access virtual processor index MSR |
| 5 |
hypercall MSRs |
| 4 |
APIC access MSRs |
| 3 |
synthetic timer MSRs |
| 2 |
basic SyncIC MSRs |
| 1 |
partition reference counter |
| 0 |
VP runtime |
| EBX |
bits |
description of flags specified at creation time (=hypercalls) |
| 31...23 |
reserved |
| 22 |
isolation (see leaf 4000_000Ch) |
| 21 |
StartVirtualProcessor |
| 20 |
EnableExtendedHypercalls |
| 19 |
reserved |
| 18 |
reserved |
| 17 |
AccessVpRegisters |
| 16 |
AccessVSM |
| 15 |
reserved |
| 14 |
reserved |
| 13 |
ConfigureProfiler |
| 12 |
CpuManagement |
| 11 |
Debugging |
| 10 |
reserved |
| 9 |
reserved |
| 8 |
AccessStats |
| 7 |
ConnectPort |
| 6 |
CreatePort |
| 5 |
SignalEvents |
| 4 |
PostMessages |
| 3 |
AdjustMessageBuffers |
| 2 |
AccessMemoryPool |
| 1 |
AccessPartitionId |
| 0 |
CreatePartition |
| ECX |
bits |
description of power management information |
| 31...11 |
reserved |
| 10 |
HV VP GHCB root mapping |
| 9 |
HV VP dispatch interrupt injection |
| 8 |
exception trap intercept |
| 7 |
architectural PMU |
| 6 |
supervisor shadow stack |
| 5 |
invariant MPERF |
| 4 |
HPET is required to enter C3 |
| 3..0 |
maximum processor power state (0=C0, 1=C1, 2=C2, 3=C3) |
| EDX |
bits |
description of miscellaneous available features |
| 31...27 |
reserved |
| 26 |
LBR |
| 25 |
reserved |
| 24 |
reserved |
| 23 |
synthetic time unhalted timer |
| 22 |
reserved |
| 21 |
BNDCFGS register for VSM |
| 20 |
PAT registers for VSM |
| 19 |
use direct synthetic timers |
| 18 |
hypercall MSR lock |
| 17 |
SintPollingMode |
| 16 |
reserved |
| 15 |
hypercall output via XMM |
| 14 |
ExtendedGvaRangesForFlushVirtualAddressList |
| 13 |
DisableHypervisor |
| 12 |
NPIEP |
| 11 |
debug MSRs |
| 10 |
guest crash MSRs |
| 9 |
inject synthetic MCs |
| 8 |
determine timer frequencies |
| 7 |
query NUMA distances |
| 6 |
hypervisior sleep state |
| 5 |
virtual guest idle state |
| 4 |
hypercall input parameter block via XMM |
| 3 |
physical CPU dynamic partitioning events |
| 2 |
performance monitor |
| 1 |
guest debugging |
| 0 |
deprecated (was: MWAIT) |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the hypervisor. |
hypervisor leaf 4000_0004h
|
|
| input |
EAX=4000_0004h |
get hypervisor information – recommendations #1 |
|
| output |
EAX |
bits |
description |
| 31...19 |
reserved |
| 18 |
NoNonArchitecturalCoreSharing (avoid STIBP overhead) |
| 17 |
use CR4.PGE toggle to flush entire TLB (when faster than hypercall) |
| 16 |
reserved |
| 15 |
UseSyncedTimeline – consume root QueryPerformanceCounter bias |
| 14 |
use nested HV using enlightened VMCS interface (see 4000_000Ah) |
| 13 |
use INT for MBEC system calls |
| 12 |
HV is nested within a Hyper-V partition |
| 11 |
newer ExProcessorMasks interface |
| 10 |
hypercall for SyntheticClusterIpi |
| 9 |
deprecate AutoEOI |
| 8 |
reserved (was: x2APIC MSRs) |
| 7 |
interrupt remapping |
| 6 |
DMA remapping |
| 5 |
relaxed timing – disable watchdogs |
| 4 |
MSR for system reset |
| 3 |
MSRs for APIC EOI/ICR/TPR |
| 2 |
hypercall for remote TLB flush |
| 1 |
hypercall for local TLB flush |
| 0 |
hypercall for address space switch |
| EBX |
bits |
description |
| 31...0 |
recommended spinlock failure retries (FFFF_FFFFh = -1 = never) |
| ECX |
bits |
description |
| 31...7 |
reserved |
| 6...0 |
ImplementedPhysicalAddressBits |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the hypervisor. |
hypervisor leaf 4000_0005h
|
|
| input |
EAX=4000_0005h |
get hypervisor information – limits #1 |
|
| output |
EAX |
bits |
description |
| 31...0 |
maximum supported virtual processors |
| EBX |
bits |
description |
| 31...0 |
maximum supported logical processors |
| ECX |
bits |
description |
| 31...0 |
maximum supported physical interrupt vectors for remapping |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the hypervisor. |
hypervisor leaf 4000_0006h
|
|
| input |
EAX=4000_0006h |
get hypervisor information – hardware features detected and in use #1 |
|
| output |
EAX |
bits |
description |
| 31...25 |
reserved |
| 24 |
ACPI WDAT table detected and in use by HV |
| 23 |
APIC emulation |
| 22 |
guest virtual IPT |
| 21 |
guest virtual LBR |
| 20 |
guest virtual PMU |
| 19 |
resource monitoring (RDT-M, PQoS-M) |
| 18 |
resource allocation (RDT-A, PQoS-A) |
| 17 |
unrestricted guest |
| 16 |
hardware memory zeroing |
| 15 |
use VMFUNC for alias map switch |
| 14 |
physical destination mode required |
| 13...10 |
HV level of current guest (0 if non-nested) |
| 9 |
synthetic timers are volatile |
| 8 |
HPET is requested |
| 7 |
DMA protection is in use |
| 6 |
memory patrol scrubber |
| 5 |
interrupt remapping |
| 4 |
DMA remapping |
| 3 |
second level address translation |
| 2 |
architectural performance counters |
| 1 |
MSR bitmaps |
| 0 |
APIC overlay assist |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the hypervisor. |
hypervisor leaf 4000_0007h
|
|
| input |
EAX=4000_0007h |
get hypervisor information – hypervisor CPU management features #1 |
|
| output |
EAX |
bits |
description |
| 31 |
ReservedIdentityBit |
| 30...3 |
reserved |
| 2 |
PerformanceCounterSync |
| 1 |
CreateRootvirtualProcessor |
| 0 |
StartLogicalProcessor |
| EBX |
bits |
description |
| 31...3 |
reserved |
| 2 |
LogicalProcessorIdling |
| 1 |
MwaitIdleStates |
| 0 |
ProcessorPowerManagement |
| ECX |
bits |
description |
| 31...1 |
reserved |
| 0 |
RemapGuestUncached |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the hypervisor. |
hypervisor leaf 4000_0008h
|
|
| input |
EAX=4000_0008h |
get hypervisor information – hypervisor SVM features #1 |
|
| output |
EAX |
bits |
description |
| 31...11 |
MaxPasidSpacePasidCount |
| 10...1 |
reserved |
| 0 |
SvmSupported |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the hypervisor. |
hypervisor leaf 4000_0009h
|
|
| input |
EAX=4000_0009h |
get hypervisor information – nested hypervisor feature identification #1 |
|
| output |
EAX |
bits |
description |
| 31...13 |
reserved |
| 12 |
AccessReenlightenmentControls |
| 11...7 |
reserved |
| 6 |
AccessVpIndex |
| 5 |
AccessHypercallMsrs |
| 4 |
AccessIntrCtrlRegs |
| 3 |
reserved |
| 2 |
AccessSynicRegs |
| 1...0 |
reserved |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...18 |
reserved |
| 17 |
SintPollingModeAvailable |
| 16 |
reserved |
| 15 |
FastHypercallOutputAvailable |
| 14...5 |
reserved |
| 4 |
XmmRegistersForFastHypercallAvailable |
| 3...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the hypervisor. |
hypervisor leaf 4000_000Ah
|
|
| input |
EAX=4000_000Ah |
get hypervisor information – hypervisor nested virtualization features #1 |
|
| output |
EAX |
bits |
description |
| 31...23 |
reserved |
| 22 |
AMD platform enlightened TLB |
| 21 |
non-zero VMCS.GuestIa32DebugCtl (0x00002802) supported |
| 20 |
page fault class virtualization exception combining supported |
| 19 |
enlightened MSR bitmap supported |
| 18 |
HvFlushGuestPhysicalAddress{Space,List} hypercalls supported |
| 17 |
direct virtual flush hypercalls supported |
| 16 |
reserved |
| 15...8 |
enlightened VMCS version (high) |
| 7...0 |
enlightened VMCS version (low) |
| EBX |
bits |
description |
| 31...1 |
reserved |
| 0 |
{Guest,Host}PerfGlobalCtrl fields in enlightened VMCS |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the hypervisor. |
hypervisor leaf 4000_000Ch
|
|
| input |
EAX=4000_000Ch |
get hypervisor information – isolation configuration #1 |
|
| output |
EAX |
bits |
description |
| 31...1 |
reserved |
| 0 |
PV present |
| EBX |
bits |
description |
| 31...12 |
reserved |
| 11...6 |
shared GPA boundary bits |
| 5 |
shared GPA boundary active |
| 4 |
reserved |
| 3...0 |
isolation type (0=none, 1=VBS, 2=SNP, 3=TDX) |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the hypervisor. |
supervisor leaf 4C78_0001h
|
|
| input |
EAX=4C78_0001h |
get supervisor information – Linux flags |
| ECX=xxxx_xxxxh |
sub-leaf to query |
|
output
(sub 0) |
EAX |
bits |
description |
| 31...0 |
word 3 |
| EBX |
bits |
description |
| 31...0 |
word 7 |
| ECX |
bits |
description |
| 31...0 |
word 8 |
| EDX |
bits |
description |
| 31...0 |
word 11 |
|
output
(sub 1) |
EAX |
bits |
description |
| 31...0 |
word 17 |
| EBX |
bits |
description |
| 31...0 |
word 21 |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the supervisor. |
supervisor leaf 4C78_0002h
|
|
| input |
EAX=4C78_0002h |
get supervisor information – Linux bugs |
| ECX=xxxx_xxxxh |
sub-leaf to query |
|
output
(sub 0) |
EAX |
bits |
description |
| 31...0 |
word 0 |
| EBX |
bits |
description |
| 31...0 |
word 1 |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only available if implemented by the supervisor. |
extended leaf 8000_0000h
|
|
| input |
EAX=8000_0000h |
get maximum supported extended leaf and vendor ID string |
|
| output |
EAX=xxxx_xxxxh |
maximum supported extended leaf |
| EBX-EDX-ECX |
vendor ID string – optional |
| AuthenticAMD |
AMD |
| reserved |
Cyrix |
| reserved |
Centaur |
| reserved |
Intel |
| TransmetaCPU |
Transmeta |
| reserved |
National Semiconductor (GX1, GXLV, GXm) |
| Geode by NSC |
National Semiconductor (GX2) |
| reserved |
DM&P (Vortex DX3) |
| HygonGenuine |
Hygon – AMD lineage |
| reserved |
Zhaoxin – Centaur lineage |
extended leaf 8000_0001h
|
|
| input |
EAX=8000_0001h |
get processor family/model/stepping and features flags |
|
| output |
EAX=xxxx_xxxxh |
processor family/model/stepping |
| reserved |
Currently unused. Future processors may use bits 31...28. |
extended family
(added to family)
|
The extended processor family is encoded in bits 27...20. |
|
00+F |
Transmeta Efficeon
AMD K8 (Fam 8)
|
| 01+F |
AMD K8L (Fam 10h) |
| 02+F |
AMD K8 (Fam 11h) |
| 03+F |
AMD K8L (Fam 12h) |
| 04+F |
(no AMD Fam 13h) |
| 05+F |
AMD BC (Fam 14h) |
| 06+F |
AMD BD (Fam 15h) – BD PD SR XV |
| 07+F |
AMD JG (Fam 16h) |
| 08+F |
AMD ZN (Fam 17h) – Zen1 and Zen2 |
| 09+F |
AMD ZN (Fam 18h) – Hygon |
| 0A+F |
AMD ZN (Fam 19h) – Zen3 and Zen4 |
| 0B+F |
AMD ZN (Fam 1Ah) – Zen5 and Zen6 |
extended model
(concatenated with model)
|
The extended processor model is encoded in bits 19...16. |
|
0...F |
see 2-digit models below |
| reserved |
Currently unused. Future processors may use bits 15...12. |
| family |
The family is encoded in bits 11...8. |
|
5 |
AMD K5 (except SSA5)
Geode
Centaur C2 and C3
Transmeta Crusoe
|
| 6 |
AMD K6
VIA C3 (up to FMS=691h)
DM&P Vortex DX3
|
| 7 |
AMD K7 |
| F |
refer to extended family |
| model |
The model is encoded in bits 7...4. |
| AMD |
XX |
see standard leaf 0000_0001h |
| Hygon |
XX |
see standard leaf 0000_0001h |
| Geode |
4 |
GX1, GXLV, GXm |
| 5 |
GX2 |
| A |
LX |
| Centaur |
8 |
C2 |
| 9 |
C3 |
| VIA C3 |
5 |
Cyrix M2 |
| 6 |
WinChip C5A |
| 7 |
WinChip C5B (if stepping = 0...7) |
| 7 |
WinChip C5C (if stepping = 8...F) |
| – |
WinChip C5M (unreleased – C5N) |
| 8 |
WinChip C5N (if stepping = 0...7) |
| 8 |
WinChip C5X (if stepping = 8...F) |
| 9 |
WinChip C5XL (if stepping = 0...7) |
| note |
up to FMS=691h: FMS reported |
| after FMS=691h: now reserved |
| DM&P |
1 |
Vortex DX3 |
| Transmeta Crusoe |
4 |
TM3x00 and TM5x00 |
| Transmeta Efficeon |
2 |
TM8000 (130 nm) |
| 2 |
TM8000 (90 nm CMS 6.0) |
| 3 |
TM8000 (90 nm CMS 6.1+) |
| stepping |
The stepping is encoded in bits 3...0. |
| The stepping values are processor-specific. |
| EBX=x000_xxxxh |
package type |
The package type is encoded in bits 31...28. |
AMD K8L
(Fam 10h) |
0000b |
Socket F |
| 0001b |
Socket AM |
| 0010b |
Socket S1 |
| 0011b |
Socket G34 |
| 0100b |
Socket ASB2 |
| 0101b |
Socket C32 |
| other |
reserved |
AMD K8L
(Fam 12h) |
0001b |
Socket FS1 (µPGA) |
| 0010b |
Socket FM1 (PGA) |
AMD BC
(Fam 14h) |
0000b |
Socket FT1 (BGA) |
AMD BD
(Fam 15h)
extended model 0
|
0001b |
Socket AM3 |
| 0011b |
Socket G34 |
| 0101b |
Socket C32 |
AMD PD
(Fam 15h)
extended model 1
|
0000b |
Socket FP2 (BGA) |
| 0001b |
Socket FS1r2 (µPGA) |
| 0010b |
Socket FM2 (PGA) |
AMD SR
(Fam 15h)
extended model 3
|
0000b |
Socket FP3 (BGA) |
| 0001b |
Socket FM2r2 (µPGA) |
AMD XV
(Fam 15h)
extended model 6
|
0000b |
Socket FP4 (BGA) |
| 0010b |
Socket AM4 (µPGA) |
| 0011b |
Socket FM2r2 (µPGA) |
AMD XV
(Fam 15h)
extended model 7
|
0000b |
Socket FP4 (BGA) |
| 0010b |
Socket AM4 (µPGA) |
| 0100b |
Socket FT4 (BGA) |
AMD JG
(Fam 16h)
extended model 0
|
0000b |
Socket FT3 (BGA) |
| 0001b |
Socket FS1b |
AMD JG
(Fam 16h)
extended model 3
|
0000b |
Socket FT3b (BGA) |
| 0011b |
Socket FP4 |
AMD Z1/Z2
(Fam 17h)
|
0000b |
Socket FP5/FP6 |
| 0001b |
Socket FT5/FT6 |
| 0010b |
Socket AM4 |
| 0100b |
Socket SP3 |
| 0111b |
Socket SP3r2 |
| 0001b |
Socket SP4 (collides with FT5/FT6?) |
| 0011b |
Socket SP4r2 |
AMD Z3/Z4
(Fam 19h)
|
0000b |
Socket FP6 |
| 0001b |
Socket FL1 |
| 0010b |
Socket AM4 |
| 0100b |
Socket SP3/SP5 |
| 0100b |
Socket FP7 (LPDDR5) (collides with SP3/SP5?) |
| 0101b |
Socket FP7r2 (DDR5) |
| 0111b |
Socket sTRX4 |
| 1000b |
Socket SP6/TR5 |
AMD Z5/Z6
(Fam 1Ah)
|
0000b |
Socket AM5 |
| 0001b |
Socket FL1/FP8/FP11 |
| 0100b |
Socket SP5 |
| 0111b |
Socket SP6/TR5 |
| brand ID |
The brand ID is encoded in bits 15...0. |
| AMD K8 DDR1 |
ID = bits 15...6 = (value >> 6) & 3FFh
NN = bits 5...0 = value & 3Fh
for NN=1...63: XX = 22 + NN
for NN=1...30: YY = 38 + (2 * NN)
for NN=1...63: ZZ = 24 + NN
for NN=1...63: TT = 24 + NN
for NN=1...11: RR = 45 + (5 * NN)
for NN=1...31: EE = 9 + NN
|
| 00h |
engineering sample |
| 04h |
AMD Athlon 64 XX00+ |
| 05h |
AMD Athlon 64 X2 XX00+ |
| 06h |
AMD Athlon 64 FX-ZZ |
| 08h |
AMD Athlon 64 XX00+ mobile |
| 09h |
AMD Athlon 64 XX00+ mobile, low power |
| 0Ah |
AMD Turion 64 ML-XX |
| 0Bh |
AMD Turion 64 MT-XX |
| 0Ch |
AMD Opteron 1YY |
| 0Dh |
AMD Opteron 1YY |
| 0Eh |
AMD Opteron 1YY HE |
| 0Fh |
AMD Opteron 1YY EE |
| 10h |
AMD Opteron 2YY |
| 11h |
AMD Opteron 2YY |
| 12h |
AMD Opteron 2YY HE |
| 13h |
AMD Opteron 2YY EE |
| 14h |
AMD Opteron 8YY |
| 15h |
AMD Opteron 8YY |
| 16h |
AMD Opteron 8YY HE |
| 17h |
AMD Opteron 8YY EE |
| 18h |
AMD Athlon 64 EE00+ |
| 1Dh |
AMD Athlon XP-M XX00+ mobile, 32-bit |
| 1Eh |
AMD Athlon XP-M XX00+ mobile, 32-bit, low p. |
| 20h |
AMD Athlon XP XX00+, 32-bit |
| 21h |
AMD Sempron TT00+ mobile, 32-bit |
| 23h |
AMD Sempron TT00+ mobile, 32-bit, low power |
| 22h |
AMD Sempron TT00+, 32-bit |
| 26h |
AMD Sempron TT00+, 64-bit |
| 24h |
AMD Athlon 64 FX-ZZ |
| 29h |
AMD Opteron DC 1RR SE |
| 2Ah |
AMD Opteron DC 2RR SE |
| 2Bh |
AMD Opteron DC 8RR SE |
| 2Ch |
AMD Opteron DC 1RR |
| 2Dh |
AMD Opteron DC 1RR |
| 2Eh |
AMD Opteron DC 1RR HE |
| 2Fh |
AMD Opteron DC 1RR EE |
| 30h |
AMD Opteron DC 2RR |
| 31h |
AMD Opteron DC 2RR |
| 32h |
AMD Opteron DC 2RR HE |
| 33h |
AMD Opteron DC 2RR EE |
| 34h |
AMD Opteron DC 8RR |
| 35h |
AMD Opteron DC 8RR |
| 36h |
AMD Opteron DC 8RR HE |
| 37h |
AMD Opteron DC 8RR EE |
| 38h |
AMD Opteron DC 1RR |
| 39h |
AMD Opteron DC 2RR |
| 3Ah |
AMD Opteron DC 8RR |
| 3Bh |
AMD Opteron DC 1RR |
| 3Ch |
AMD Opteron DC 2RR |
| 3Dh |
AMD Opteron DC 8RR |
| other |
unknown |
| AMD K8 DDR2 |
S = socket (see CPUID model bits 1...0)
CC = core count - 1 (see NB capabilities reg)
ID = bits 13...9
PL = bits 8...6 and 14
NN = bits 15 and 5...0
RR = -1 + NN*
PP = 26 + NN
TT = 15 + (CC * 10) + NN
ZZ = 57 + NN**
YY = 29 + NN
* 000001b...000010b/100010b...111111b = 1...2/34...63 are reserved
** 100010b...111111b = 34...63 are reserved
|
| S=any CC=? ID=00h PL=0h |
engineering sample |
| S=AM2 CC=0 ID=01h PL=5h |
AMD Sempron LE-1RR0 |
| S=AM2 CC=0 ID=02h PL=6h |
AMD Athlon LE-1ZZ0 |
| S=AM2 CC=0 ID=03h PL=6h |
AMD Athlon 1ZZ0B |
| S=AM2 CC=0 ID=04h PL=1h |
AMD Athlon 64 TT00+ |
| S=AM2 CC=0 ID=04h PL=2h |
AMD Athlon 64 TT00+ |
| S=AM2 CC=0 ID=04h PL=3h |
AMD Athlon 64 TT00+ |
| S=AM2 CC=0 ID=04h PL=4h |
AMD Athlon 64 TT00+ |
| S=AM2 CC=0 ID=04h PL=5h |
AMD Athlon 64 TT00+ |
| S=AM2 CC=0 ID=04h PL=8h |
AMD Athlon 64 TT00+ |
| S=AM2 CC=0 ID=05h PL=2h |
AMD Sempron RR50p |
| S=AM2 CC=0 ID=06h PL=4h |
AMD Sempron TT00+ |
| S=AM2 CC=0 ID=06h PL=8h |
AMD Sempron TT00+ |
| S=ASB1 CC=0 ID=07h PL=1h |
AMD Sempron TT0U |
| S=ASB1 CC=0 ID=07h PL=2h |
AMD Sempron TT0U |
| S=AM2 CC=0 ID=08h PL=2h |
AMD Athlon TT50e |
| S=AM2 CC=0 ID=08h PL=3h |
AMD Athlon TT50e |
| S=ASB1 CC=0 ID=09h PL=2h |
AMD Athlon Neo MV-TT |
| S=ASB1 CC=0 ID=0Ch PL=2h |
AMD Sempron 2RRU |
| S=AM2 CC=1 ID=01h PL=6h |
AMD Opteron DC 12RR HE |
| S=AM2 CC=1 ID=01h PL=Ah |
AMD Opteron DC 12RR |
| S=AM2 CC=1 ID=01h PL=Ch |
AMD Opteron DC 12RR SE |
| S=AM2 CC=1 ID=03h PL=3h |
AMD Athlon X2 BE-2TT0 |
| S=AM2 CC=1 ID=04h PL=1h |
AMD Athlon 64 X2 TT00+ |
| S=AM2 CC=1 ID=04h PL=2h |
AMD Athlon 64 X2 TT00+ |
| S=AM2 CC=1 ID=04h PL=6h |
AMD Athlon 64 X2 TT00+ |
| S=AM2 CC=1 ID=04h PL=8h |
AMD Athlon 64 X2 TT00+ |
| S=AM2 CC=1 ID=04h PL=Ch |
AMD Athlon 64 X2 TT00+ |
| S=AM2 CC=1 ID=05h PL=Ch |
AMD Athlon 64 FX-ZZ |
| S=AM2 CC=1 ID=06h PL=6h |
AMD Sempron RR00 |
| S=AM2 CC=1 ID=07h PL=3h |
AMD Athlon TT50e |
| S=AM2 CC=1 ID=07h PL=6h |
AMD Athlon TT00B |
| S=AM2 CC=1 ID=07h PL=7h |
AMD Athlon TT00B |
| S=AM2 CC=1 ID=08h PL=3h |
AMD Athlon TT50B |
| S=AM2 CC=1 ID=09h PL=1h |
AMD Athlon X2 TT50e |
| S=AM2 CC=1 ID=0Ah PL=1h |
AMD Athlon Neo X2 TT50e |
| S=AM2 CC=1 ID=0Ah PL=2h |
AMD Athlon Neo X2 TT50e |
| S=ASB1 CC=1 ID=0Bh PL=0h |
AMD Turion Neo X2 L6RR |
| S=ASB1 CC=1 ID=0Ch PL=0h |
AMD Athlon Neo X2 L3RR |
| S=S1 CC=0 ID=01h PL=2h |
AMD Athlon 64 TT00+ |
| S=S1 CC=0 ID=02h PL=Ch |
AMD Turion 64 MK-YY |
| S=S1 CC=0 ID=03h PL=1h |
AMD Sempron TT00+ mobile |
| S=S1 CC=0 ID=03h PL=6h |
AMD Sempron PP00+ mobile |
| S=S1 CC=0 ID=03h PL=Ch |
AMD Sempron PP00+ mobile |
| S=S1 CC=0 ID=04h PL=2h |
AMD Sempron TT00+ |
| S=S1 CC=0 ID=06h PL=4h |
AMD Athlon TF-TT |
| S=S1 CC=0 ID=06h PL=6h |
AMD Athlon TF-TT |
| S=S1 CC=0 ID=06h PL=Ch |
AMD Athlon TF-TT |
| S=S1 CC=0 ID=07h PL=3h |
AMD Athlon L1RR |
| S=S1 CC=1 ID=01h PL=Ch |
AMD Sempron TJ-YY |
| S=S1 CC=1 ID=02h PL=Ch |
AMD Turion 64 X2 TL-YY |
| S=S1 CC=1 ID=03h PL=4h |
AMD Athlon 64 X2 TK-YY |
| S=S1 CC=1 ID=03h PL=Ch |
AMD Athlon 64 X2 TK-YY |
| S=S1 CC=1 ID=05h PL=4h |
AMD Athlon 64 X2 TT00+ |
| S=S1 CC=1 ID=06h PL=2h |
AMD Athlon X2 L3RR |
| S=S1 CC=1 ID=07h PL=4h |
AMD Turion X2 L5RR |
| S=F1207 CC=0 ID=01h PL=2h |
AMD Opteron 22RR EE |
| S=F1207 CC=1 ID=00h PL=2h |
AMD Opteron DC 12RR EE |
| S=F1207 CC=1 ID=00h PL=6h |
AMD Opteron DC 12RR HE |
| S=F1207 CC=1 ID=01h PL=2h |
AMD Opteron DC 22RR EE |
| S=F1207 CC=1 ID=01h PL=6h |
AMD Opteron DC 22RR HE |
| S=F1207 CC=1 ID=01h PL=Ah |
AMD Opteron DC 22RR |
| S=F1207 CC=1 ID=01h PL=Ch |
AMD Opteron DC 22RR SE |
| S=F1207 CC=1 ID=04h PL=2h |
AMD Opteron DC 82RR EE |
| S=F1207 CC=1 ID=04h PL=6h |
AMD Opteron DC 82RR HE |
| S=F1207 CC=1 ID=04h PL=Ah |
AMD Opteron DC 82RR |
| S=F1207 CC=1 ID=04h PL=Ch |
AMD Opteron DC 82RR SE |
| S=F1207 CC=1 ID=06h PL=Eh |
AMD Athlon 64 FX-ZZ (Fr3) |
AMD K8L
(Fam 10h) |
PT = package type (se EBX bits 31...28)
NC = number of cores (see leaf 8000_0008h)
PG = bit 15
S1 = bits 14...11
M = bits 10...4
S2 = bits 3...0
|
| PT=0 PG=0 NC=3 S1=0h |
QC AMD Opteron Processor 83 |
| PT=0 PG=0 NC=3 S1=1h |
QC AMD Opteron Processor 23 |
| PT=0 PG=0 NC=5 S1=0h |
6C AMD Opteron Processor 84 |
| PT=0 PG=0 NC=5 S1=1h |
6C AMD Opteron Processor 24 |
| PT=0 PG=1 NC=3 S1=1h |
Embedded AMD Opteron Processor_ |
| PT=0 PG=1 NC=5 S1=1h |
Embedded AMD Opteron Processor_ |
| PT=0 PG=0 NC=3 S2=Ah |
SE |
| PT=0 PG=0 NC=3 S2=Bh |
HE |
| PT=0 PG=0 NC=3 S2=Ch |
EE |
| PT=0 PG=0 NC=5 S2=0h |
SE |
| PT=0 PG=0 NC=5 S2=1h |
HE |
| PT=0 PG=0 NC=5 S2=2h |
EE |
| PT=0 PG=0 NC=x S2=Fh |
(empty) |
| PT=0 PG=1 NC=3 S2=1h |
GF HE |
| PT=0 PG=1 NC=3 S2=2h |
HF HE |
| PT=0 PG=1 NC=3 S2=3h |
VS |
| PT=0 PG=1 NC=3 S2=4h |
QS HE |
| PT=0 PG=1 NC=3 S2=5h |
NP HE |
| PT=0 PG=1 NC=3 S2=6h |
KH HE |
| PT=0 PG=1 NC=3 S2=7h |
KS EE |
| PT=0 PG=1 NC=5 S2=1h |
QS |
| PT=0 PG=1 NC=5 S2=2h |
KS HE |
| PT=1 PG=0 NC=0 S1=2h |
AMD Sempron 1 |
| PT=1 PG=0 NC=0 S1=3h |
AMD Athlon II 1 |
| PT=1 PG=0 NC=1 S1=1h |
AMD Athlon_ |
| PT=1 PG=0 NC=1 S1=3h |
AMD Athlon II X2 2 |
| PT=1 PG=0 NC=1 S1=4h |
AMD Athlon II X2 B |
| PT=1 PG=0 NC=1 S1=5h |
AMD Athlon II X2_ |
| PT=1 PG=0 NC=1 S1=7h |
AMD Phenom II X2 5 |
| PT=1 PG=0 NC=1 S1=Ah |
AMD Phenom II X2_ |
| PT=1 PG=0 NC=1 S1=Bh |
AMD Phenom II X2 B |
| PT=1 PG=0 NC=1 S1=Ch |
AMD Sempron X2 1 |
| PT=1 PG=0 NC=2 S1=0h |
AMD Phenom_ |
| PT=1 PG=0 NC=2 S1=3h |
AMD Phenom II X3 B |
| PT=1 PG=0 NC=2 S1=4h |
AMD Phenom II X3_ |
| PT=1 PG=0 NC=2 S1=7h |
AMD Athlon II X3 4 |
| PT=1 PG=0 NC=2 S1=8h |
AMD Phenom II X3 7 |
| PT=1 PG=0 NC=2 S1=Ah |
AMD Athlon II X3_ |
| PT=1 PG=0 NC=3 S1=0h |
QC AMD Opteron Processor 13 |
| PT=1 PG=0 NC=3 S1=2h |
AMD Phenom_ |
| PT=1 PG=0 NC=3 S1=3h |
AMD Phenom II X4 9 |
| PT=1 PG=0 NC=3 S1=4h |
AMD Phenom II X4 8 |
| PT=1 PG=0 NC=3 S1=7h |
AMD Phenom II X4 B |
| PT=1 PG=0 NC=3 S1=8h |
AMD Phenom II X4_ |
| PT=1 PG=0 NC=3 S1=Ah |
AMD Athlon II X4 6 |
| PT=1 PG=0 NC=3 S1=Fh |
AMD Athlon II X4_ |
| PT=1 PG=0 NC=5 S1=0h |
AMD Phenom II X6 1 |
| PT=1 PG=1 NC=1 S1=1h |
AMD Athlon II XLT V |
| PT=1 PG=1 NC=1 S1=2h |
AMD Athlon II XL V |
| PT=1 PG=1 NC=3 S1=1h |
AMD Phenom II XLT Q |
| PT=1 PG=1 NC=3 S1=2h |
AMD Phenom II X4 9 |
| PT=1 PG=1 NC=3 S1=3h |
AMD Phenom II X4 8 |
| PT=1 PG=1 NC=3 S1=4h |
AMD Phenom II X4 6 |
| PT=1 PG=0 NC=0 S2=Ah |
Processor |
| PT=1 PG=0 NC=0 S2=Bh |
u Processor |
| PT=1 PG=0 NC=1 S2=3h |
50 DC Processor |
| PT=1 PG=0 NC=1 S2=6h |
Processor |
| PT=1 PG=0 NC=1 S2=7h |
e Processor |
| PT=1 PG=0 NC=1 S2=9h |
0 Processor |
| PT=1 PG=0 NC=1 S2=Ah |
0e Processor |
| PT=1 PG=0 NC=1 S2=Bh |
u Processor |
| PT=1 PG=0 NC=2 S2=0h |
00 3C Processor |
| PT=1 PG=0 NC=2 S2=1h |
00e 3C Processor |
| PT=1 PG=0 NC=2 S2=2h |
00B 3C Processor |
| PT=1 PG=0 NC=2 S2=3h |
50 3C Processor |
| PT=1 PG=0 NC=2 S2=4h |
50e 3C Processor |
| PT=1 PG=0 NC=2 S2=5h |
50B 3C Processor |
| PT=1 PG=0 NC=2 S2=6h |
Processor |
| PT=1 PG=0 NC=2 S2=7h |
e Processor |
| PT=1 PG=0 NC=2 S2=9h |
0e Processor |
| PT=1 PG=0 NC=2 S2=Ah |
0 Processor |
| PT=1 PG=0 NC=3 S2=0h |
00 QC Processor |
| PT=1 PG=0 NC=3 S2=1h |
00e QC Processor |
| PT=1 PG=0 NC=3 S2=2h |
00B QC Processor |
| PT=1 PG=0 NC=3 S2=3h |
50 QC Processor |
| PT=1 PG=0 NC=3 S2=4h |
50e QC Processor |
| PT=1 PG=0 NC=3 S2=5h |
50B QC Processor |
| PT=1 PG=0 NC=3 S2=6h |
Processor |
| PT=1 PG=0 NC=3 S2=7h |
e Processor |
| PT=1 PG=0 NC=3 S2=9h |
0e Processor |
| PT=1 PG=0 NC=3 S2=Eh |
0 Processor |
| PT=1 PG=0 NC=5 S2=0h |
5T Processor |
| PT=1 PG=0 NC=5 S2=1h |
0T Processor |
| PT=1 PG=0 NC=x S2=Fh |
(empty) |
| PT=1 PG=1 NC=1 S2=1h |
L Processor |
| PT=1 PG=1 NC=1 S2=2h |
C Processor |
| PT=1 PG=1 NC=3 S2=1h |
L Processor |
| PT=1 PG=1 NC=3 S2=4h |
T Processor |
| PT=2 PG=0 NC=0 S1=0h |
AMD Sempron M1 |
| PT=2 PG=0 NC=0 S1=1h |
AMD V |
| PT=2 PG=0 NC=1 S1=0h |
AMD Turion II Ultra DC Mobile M6 |
| PT=2 PG=0 NC=1 S1=1h |
AMD Turion II DC Mobile M5 |
| PT=2 PG=0 NC=1 S1=2h |
AMD Athlon II DC M3 |
| PT=2 PG=0 NC=1 S1=3h |
AMD Turion II P |
| PT=2 PG=0 NC=1 S1=4h |
AMD Athlon II P |
| PT=2 PG=0 NC=1 S1=5h |
AMD Phenom II X |
| PT=2 PG=0 NC=1 S1=6h |
AMD Phenom II N |
| PT=2 PG=0 NC=1 S1=7h |
AMD Turion II N |
| PT=2 PG=0 NC=1 S1=8h |
AMD Athlon II N |
| PT=2 PG=0 NC=1 S1=9h |
AMD Phenom II P |
| PT=2 PG=0 NC=2 S1=2h |
AMD Phenom II P |
| PT=2 PG=0 NC=2 S1=3h |
AMD Phenom II N |
| PT=2 PG=0 NC=2 S1=4h |
AMD Phenom II X |
| PT=2 PG=0 NC=3 S1=1h |
AMD Phenom II P |
| PT=2 PG=0 NC=3 S1=2h |
AMD Phenom II X |
| PT=2 PG=0 NC=3 S1=3h |
AMD Phenom II N |
| PT=2 PG=0 NC=0 S2=1h |
0 Processor |
| PT=2 PG=0 NC=1 S2=2h |
0 DC Processor |
| PT=2 PG=0 NC=2 S2=2h |
0 3C Processor |
| PT=2 PG=0 NC=3 S2=1h |
0 QC Processor |
| PT=2 PG=0 NC=x S2=Fh |
(empty) |
| PT=3 PG=0 NC=7 S1=0h |
AMD Opteron Processor 61 |
| PT=3 PG=0 NC=B S1=0h |
AMD Opteron Processor 61 |
| PT=3 PG=1 NC=7 S1=1h |
Embedded AMD Opteron Processor_ |
| PT=3 PG=0 NC=7 S2=0h |
HE |
| PT=3 PG=0 NC=7 S2=1h |
SE |
| PT=3 PG=0 NC=B S2=0h |
HE |
| PT=3 PG=0 NC=B S2=1h |
SE |
| PT=3 PG=0 NC=x S2=Fh |
(empty) |
| PT=3 PG=1 NC=7 S2=1h |
QS |
| PT=3 PG=1 NC=7 S2=2h |
KS |
| PT=4 PG=0 NC=0 S1=1b |
AMD Athlon II Neo K |
| PT=4 PG=0 NC=0 S1=2b |
AMD V |
| PT=4 PG=0 NC=0 S1=3b |
AMD Athlon II Neo R |
| PT=4 PG=0 NC=1 S1=1b |
AMD Turion II Neo K |
| PT=4 PG=0 NC=1 S1=2b |
AMD Athlon II Neo K |
| PT=4 PG=0 NC=1 S1=3b |
AMD V |
| PT=4 PG=0 NC=1 S1=4b |
AMD Turion II Neo N |
| PT=4 PG=0 NC=1 S1=5b |
AMD Athlon II Neo N |
| PT=4 PG=0 NC=0 S2=1h |
5 Processor |
| PT=4 PG=0 NC=0 S2=2h |
L Processor |
| PT=4 PG=0 NC=1 S2=1h |
5 DC Processor |
| PT=4 PG=0 NC=1 S2=2h |
L DC Processor |
| PT=4 PG=0 NC=1 S2=4h |
H DC Processor |
| PT=4 PG=0 NC=x S2=Fh |
(empty) |
| PT=5 PG=0 NC=3 S1=0h |
AMD Opteron Processor 41 |
| PT=5 PG=0 NC=5 S1=0h |
AMD Opteron Processor 41 |
| PT=5 PG=1 NC=3 S1=1h |
Embedded AMD Opteron Processor_ |
| PT=5 PG=1 NC=5 S1=1h |
Embedded AMD Opteron Processor_ |
| PT=5 PG=0 NC=3 S2=0h |
HE |
| PT=5 PG=0 NC=3 S2=1h |
EE |
| PT=5 PG=0 NC=5 S2=0h |
HE |
| PT=5 PG=0 NC=5 S2=1h |
EE |
| PT=5 PG=0 NC=x S2=Fh |
(empty) |
| PT=5 PG=1 NC=3 S2=1h |
QS HE |
| PT=5 PG=1 NC=3 S2=2h |
LE HE |
| PT=5 PG=1 NC=3 S2=3h |
CL EE |
| PT=5 PG=1 NC=5 S2=1h |
KX HE |
| PT=5 PG=1 NC=5 S2=2h |
GL EE |
AMD K8L
(Fam 11h) |
PT = package type (se EBX bits 31...28)
NC = number of cores (see leaf 8000_0008h)
PG = bit 15
S1 = bits 14...11
M = bits 10...4
S2 = bits 3...0
|
| PT=2 PG=0 NC=0 S1=0h |
AMD Sempron SI- |
| PT=2 PG=0 NC=0 S1=1h |
AMD Athlon QI- |
| PT=2 PG=0 NC=1 S1=0h |
AMD Turion X2 Ultra Dual-Core Mobile ZM- |
| PT=2 PG=0 NC=1 S1=1h |
AMD Turion X2 Dual-Core Mobile RM- |
| PT=2 PG=0 NC=1 S1=2h |
AMD Athlon X2 Dual-Core QL- |
| PT=2 PG=0 NC=1 S1=3h |
AMD Sempron X2 Dual-Core NI- |
| PT=2 PG=0 NC=0 S2=0h |
(empty) |
| PT=2 PG=0 NC=1 S2=0h |
(empty) |
| PT=2 PG=0 NC=x S2=Fh |
(empty) |
AMD K8L
(Fam 12h) |
PT = package type (se EBX bits 31...28)
NC = number of cores (see leaf 8000_0008h)
PG = bit 15
S1 = bits 14...11
M = bits 10...4
S2 = bits 3...0
|
| PT=1 PG=0 NC=1 S1=3h |
AMD A4-33 |
| PT=1 PG=0 NC=1 S1=5h |
AMD E2-30 |
| PT=1 PG=0 NC=4 S1=1h |
AMD A8-35 |
| PT=1 PG=0 NC=4 S1=3h |
AMD A6-34 |
| PT=1 PG=0 NC=1 S2=1h |
M APU with Radeon HD Graphics |
| PT=1 PG=0 NC=1 S2=2h |
MX APU with Radeon HD Graphics |
| PT=1 PG=0 NC=3 S2=1h |
M APU with Radeon HD Graphics |
| PT=1 PG=0 NC=3 S2=2h |
MX APU with Radeon HD Graphics |
| PT=1 PG=0 NC=x S2=Fh |
(empty) |
| PT=2 PG=0 NC=1 S1=1h |
AMD A4-33 |
| PT=2 PG=0 NC=1 S1=2h |
AMD E2-32 |
| PT=2 PG=0 NC=1 S1=4h |
AMD Athlon II X2 2 |
| PT=2 PG=0 NC=1 S1=5h |
AMD A4-34 |
| PT=2 PG=0 NC=1 S1=Ch |
AMD Sempron X2 1 |
| PT=2 PG=0 NC=2 S1=5h |
AMD A6-35 |
| PT=2 PG=0 NC=3 S1=5h |
AMD A8-38 |
| PT=2 PG=0 NC=3 S1=6h |
AMD A6-36 |
| PT=2 PG=0 NC=3 S1=Dh |
AMD Athlon II X4 6 |
| PT=2 PG=0 NC=1 S1=1h |
APU with Radeon HD Graphics |
| PT=2 PG=0 NC=1 S1=2h |
Dual-Core Processor |
| PT=2 PG=0 NC=2 S1=1h |
APU with Radeon HD Graphics |
| PT=2 PG=0 NC=3 S1=1h |
APU with Radeon HD Graphics |
| PT=2 PG=0 NC=3 S1=3h |
Quad-Core Processor |
| PT=2 PG=0 NC=x S1=Fh |
(empty) |
AMD BC
(Fam 14h) |
PT = package type (se EBX bits 31...28)
NC = number of cores (see leaf 8000_0008h)
PG = bit 15
S1 = bits 14...11
M = bits 10...4
S2 = bits 3...0
|
| PT=0 PG=0 NC=0 S1=1h |
AMD C- (client) |
| PT=0 PG=0 NC=0 S1=2h |
AMD E- (client) |
| PT=0 PG=0 NC=0 S1=4h |
AMD G-T- (embedded) |
| PT=0 PG=0 NC=1 S1=1h |
AMD C- (client) |
| PT=0 PG=0 NC=1 S1=2h |
AMD E- (client) |
| PT=0 PG=0 NC=1 S1=3h |
AMD Z- (tablet) |
| PT=0 PG=0 NC=1 S1=4h |
AMD G-T- (embedded) |
| PT=0 PG=0 NC=1 S1=5h |
AMD E1-1- (client) |
| PT=0 PG=0 NC=1 S1=6h |
AMD E2-1- (client) |
| PT=0 PG=0 NC=1 S1=7h |
AMD E2-2- (client) |
| PT=0 PG=0 NC=0 S2=1h |
Processor |
| PT=0 PG=0 NC=0 S2=2h |
0 Processor |
| PT=0 PG=0 NC=0 S2=3h |
5 Processor |
| PT=0 PG=0 NC=0 S2=4h |
0x Processor |
| PT=0 PG=0 NC=0 S2=5h |
5x Processor |
| PT=0 PG=0 NC=0 S2=6h |
x Processor |
| PT=0 PG=0 NC=0 S2=7h |
L Processor |
| PT=0 PG=0 NC=0 S2=8h |
N Processor |
| PT=0 PG=0 NC=0 S2=9h |
R Processor |
| PT=0 PG=0 NC=0 S2=Ah |
0 APU with Radeon HD Graphics |
| PT=0 PG=0 NC=0 S2=Bh |
5 APU with Radeon HD Graphics |
| PT=0 PG=0 NC=0 S2=Ch |
APU with Radeon HD Graphics |
| PT=0 PG=0 NC=0 S2=Dh |
0D APU with Radeon HD Graphics |
| PT=0 PG=0 NC=1 S2=1h |
Processor |
| PT=0 PG=0 NC=1 S2=2h |
0 Processor |
| PT=0 PG=0 NC=1 S2=3h |
5 Processor |
| PT=0 PG=0 NC=1 S2=4h |
0x Processor |
| PT=0 PG=0 NC=1 S2=5h |
5x Processor |
| PT=0 PG=0 NC=1 S2=6h |
x Processor |
| PT=0 PG=0 NC=1 S2=7h |
L Processor |
| PT=0 PG=0 NC=1 S2=8h |
N Processor |
| PT=0 PG=0 NC=1 S2=9h |
0 APU with Radeon HD Graphics |
| PT=0 PG=0 NC=1 S2=Ah |
5 APU with Radeon HD Graphics |
| PT=0 PG=0 NC=1 S2=Bh |
APU with Radeon HD Graphics |
| PT=0 PG=0 NC=1 S2=Ch |
E Processor |
| PT=0 PG=0 NC=1 S2=Dh |
0D APU with Radeon HD Graphics |
| PT=0 PG=0 NC=x S2=Fh |
(empty) |
| ECX=xxxx_xxxxh |
feature flags |
description of indicated feature |
| 31 |
reserved |
| 30 (AddrMaskExt) |
breakpoint addressing making extended to bit 31 |
| 29 (MONX) |
MONITORX/MWAITX |
| 28 (PCX_L2I / L3) |
L2I perf counter extensions (MSRs C001_023[0...7]h) (Fam 15h/16h)
L3 perf counter extensions (MSRs C001_023[0...B]h) (Fam 17h)
|
| 27 (PERFTSC) |
performance TSC (MSR C001_0280h) |
| 26 (DBX) |
data breakpoint extensions (MSRs C001_1027h + C001_10[19...1B]h) |
| 25 (STR_PERF) |
streaming performance monitor |
| 24 (PCX_NB) |
NB perf counter extensions (MSRs C001_024[0...7]h) |
| 23 (PCX_CORE) |
core perf counter extensions (MSRs C001_020[0...B]h) |
| 22 (TOPX) |
topology extensions: extended leaves 8000_001Dh and 8000_001Eh |
| 21 (TBM) |
TBM |
| 20 |
reserved |
| 19 (NODEID) |
node ID: MSR C001_100Ch |
| 18 (CVT16) |
CVT16 |
| 17 (TCE) |
translation cache extension, EFER.TCE |
| 16 (FMA4) |
FMA4 |
| 15 (LWP) |
LWP |
| 14 (TBM0) |
TBM0 |
| 13 (WDT) |
watchdog timer |
| 12 (SKINIT) |
SKINIT, STGI, DEV |
| 11 (XOP) |
XOP (was also used going to be used for SSE5A) |
| 10 (IBS) |
instruction based sampling |
| 9 (OSVW) |
OS-visible workaround |
| 8 (3DNow!P) |
PREFETCH and PREFETCHW (K8 Rev G and K8L+) |
| 7 (MSSE) |
misaligned SSE, MXCSR.MM |
| 6 (SSE4A) |
SSE4A |
| 5 (LZCNT) |
LZCNT |
| 4 (CR8D) |
MOV from/to CR8D by means of LOCK-prefixed MOV from/to CR0 |
| 3 (EAS) |
extended APIC space (APIC_VER.EAS, EXT_APIC_FEAT, etc.) |
| 2 (SVM) |
EFER.SVME
VMRUN, VMMCALL, VMLOAD and VMSAVE, STGI and CLGI,
SKINIT, INVLPGA
|
| 1 (CMP) |
HTT=1 indicates HTT (0) or CMP (1) |
| 0 (AHF64) |
LAHF and SAHF in PM64 |
| EDX=xxxx_xxxxh |
feature flags |
description of indicated feature |
| 31 (3DNow!) |
3DNow! |
| 30 (3DNow!+) |
extended 3DNow! |
| 29 (LM) |
AMD64/EM64T, Long Mode |
| 28 (REX32) |
REX32 mode (PM32REX and CM32REX) (initially supported by AMD K8 processors)
HWCR.REX32EN, EFER.REX32, EFLAGS.RX32,
CLX and STX, MOVSXD, FXSR R8-R15
|
| 27 (TSCP) |
TSC, TSC_AUX, RDTSCP, CR4.TSD |
| 26 (PG1G) |
PML3E.PS |
| 25 (FFXSR) |
EFER.FFXSR |
24 (MMX+)
24 (FXSR)
|
Cyrix specific: extended MMX
AMD K7: FXSAVE/FXRSTOR, CR4.OSFXSR
|
| 23 (MMX) |
MMX |
| 22 (MMX+) |
AMD specific: MMX-SSE and SSE-MEM |
| 21 |
reserved |
| 20 (NX) |
EFER.NXE, P?E.NX, #PF(1xxxx) (Intel calls it XD) (MSFT calls it Hardware DEP) |
| 19 (MP) |
MP-capable #3 |
| 18 |
reserved |
| 17 (PSE36) |
4 MB PDE bits 16...13, CR4.PSE |
16 (PAT)
16 (FCMOV)
|
PAT MSR, PDE/PTE.PAT
AMD pre-K7: FCMOVcc/F(U)COMI(P) (implies FPU=1)
|
| 15 (CMOV) |
CMOVcc |
| 14 (MCA) |
MCG_*/MCn_* MSRs, CR4.MCE, #MC |
| 13 (PGE) |
PDE/PTE.G, CR4.PGE |
| 12 (MTRR) |
MTRR* MSRs |
| 11 (SEP) |
SYSCALL/SYSRET, EFER/STAR MSRs #1 |
| 10 |
reserved #1 |
| 9 (APIC) |
APIC #2 |
| 8 (CX8) |
CMPXCHG8B |
| 7 (MCE) |
MCAR/MCTR MSRs, CR4.MCE, #MC |
| 6 (PAE) |
64-bit PDPTE/PDE/PTEs, CR4.PAE |
| 5 (MSR) |
MSRs, RDMSR/WRMSR |
| 4 (TSC) |
TSC, RDTSC, CR4.TSD (doesn't imply MSR=1) |
| 3 (PSE) |
PDE.PS, PDE/PTE.res, CR4.PSE, #PF(1xxxb) |
| 2 (DE) |
CR4.DE, DR7.RW=10b, #UD on MOV from/to DR4/5 |
| 1 (VME) |
CR4.VME/PVI, EFLAGS.VIP/VIF, TSS32.IRB |
| 0 (FPU) |
FPU |
|
| notes |
descriptions |
|
| #1 |
The AMD K6 processor, model 6, uses bit 10 to indicate SEP. Beginning with model 7, bit 11 is used instead. |
| Intel processors only report SEP when CPUID is executed in PM64. |
| #2 |
If the APIC has been disabled, then the APIC feature flag will read as 0. |
| #3 |
AMD K7 processors prior to CPUID=0662h may report 0 even if they are MP-capable. |
extended leaves 8000_0002h, 8000_0003h, and 8000_0004h
|
|
| input |
EAX=8000_0002h |
get processor name string (part 1) |
| EAX=8000_0003h |
get processor name string (part 2) |
| EAX=8000_0004h |
get processor name string (part 3) |
|
| output |
EAX
EBX
ECX
EDX
|
processor name string #1 |
| AMD K5 |
AMD-K5(tm) Processor |
| AMD K6 |
AMD-K6tm w/ multimedia extensions |
| AMD K6-2 |
AMD-K6(tm) 3D processor
AMD-K6(tm)-2 Processor
|
| AMD K6-III |
AMD-K6(tm) 3D+ Processor
AMD-K6(tm)-III Processor
|
| AMD K6-2+ |
AMD-K6(tm)-III Processor (?) |
| AMD K6-III+ |
AMD-K6(tm)-III Processor (?) |
| AMD K7 |
AMD-K7(tm) Processor (model 1)
AMD Athlon(tm) Processor (model 2)
newer models: programmable
|
| AMD K8 |
programmable via MSRs C001_0030h...C001_0035h, default is 48x 0 |
| AMD K8L |
programmable via MSRs C001_0030h...C001_0035h, default is 48x 0 |
| AMD BC |
programmable via MSRs C001_0030h...C001_0035h, default is 48x 0 |
| Geode GX2 |
Geode(TM) Integrated Processor by National Semi
programmable via MSRs 0000_300Ah...0000_300Fh
|
| Geode LX |
Geode(TM) Integrated Processor by AMD PCS
programmable via MSRs 0000_300Ah...0000_300Fh
|
| Centaur C2 #2 |
IDT WinChip 2
IDT WinChip 2-3D
|
| Centaur C3 |
IDT WinChip 3 |
| VIA C3 |
CYRIX III(tm) (?)
VIA Samuel (?)
VIA Ezra (?)
VIA C3 Nehemiah (?)
|
| Intel PM #3 |
Intel(R) Pentium(R) M processor xxxxMHz |
| Intel P4 #3 |
Intel(R) Pentium(R) 4 CPU xxxxMHz |
| Intel Core 2 |
Intel(R) Xeon(R) CPU xxxx @ x.xxGHz |
| Transmeta Crusoe |
Transmeta(tm) Crusoe(tm) Processor TMxxxx |
| Transmeta Efficeon |
Transmeta Efficeon(tm) Processor TM8000 |
|
| notes |
descriptions |
|
| #1 |
Unused characters at the end of the string are filled with 00h. |
| #2 |
The string depends on whether 3DNow! is disabled or enabled. |
| #3 |
The string is right-justified, with leading whitespaces. |
extended leaf 8000_0005h
|
|
| input |
EAX=8000_0005h |
get L1 cache and L1 TLB configuration descriptors #1 |
|
| output |
EAX |
4/2 MB L1 TLB configuration descriptor |
| bits |
description |
| 31...24 |
data TLB associativity (FFh=full) |
| 23...16 |
data TLB entries |
| 15...8 |
code TLB associativity (FFh=full) |
| 7...0 |
code TLB entries |
| EBX |
4 KB L1 TLB configuration descriptor #2 |
| bits |
description |
| 31...24 |
data TLB associativity (FFh=full) |
| 23...16 |
data TLB entries |
| 15...8 |
code TLB associativity (FFh=full) |
| 7...0 |
code TLB entries |
| ECX |
data L1 cache configuration descriptor |
| bits |
description |
| 31...24 |
data L1 cache size in KBs |
| 23...16 |
data L1 cache associativity (FFh=full) |
| 15...8 |
data L1 cache lines per tag |
| 7...0 |
data L1 cache line size in bytes |
| EDX |
code L1 cache configuration descriptor |
| bits |
description |
| 31...24 |
code L1 cache size in KBs |
| 23...16 |
code L1 cache associativity (FFh=full) |
| 15...8 |
code L1 cache lines per tag |
| 7...0 |
code L1 cache line size in bytes |
|
| notes |
descriptions |
|
| #1 |
Cyrix processors return CPUID leaf 0000_0002h-like descriptors instead. (Though the NS Geode GX2 does not.) |
| #2 |
While Transmeta Crusoe processors have 256 entries, the CPUID definition constrains them to reporting only 255.
For compatibility reasons they report their unified TLB twice: once for the code TLB, and once for the data TLB.
|
extended leaf 8000_0006h
|
|
| input |
EAX=8000_0006h |
get L2/L3 cache and L2 TLB configuration descriptors |
|
| output |
EAX |
4/2 MB L2 TLB configuration descriptor #1 |
| bits |
description |
| 31...28 |
data TLB associativity #2 |
| 27...16 |
data TLB entries |
| 15...12 |
code TLB associativity #2 |
| 11...0 |
code TLB entries |
| EBX |
4 KB L2 TLB configuration descriptor #1 |
| bits |
description |
| 31...28 |
data TLB associativity #2 |
| 27...16 |
data TLB entries |
| 15...12 |
code TLB associativity #2 |
| 11...0 |
code TLB entries |
| ECX |
unified L2 cache configuration descriptor #3 |
| bits |
description |
| 31...16 #5 |
unified L2 cache size in KBs #4 |
| 15...12 #5 |
unified L2 cache associativity #2, #6 |
| 11...8 #5 |
unified L2 cache lines per tag |
| 7...0 |
unified L2 cache line size in bytes |
| EDX |
unified L3 cache configuration descriptor |
| bits |
description |
| 31...18 |
unified L3 cache size in 512 KB chunks |
| 17...16 |
reserved |
| 15...12 |
unified L3 cache associativity #2 |
| 11...8 |
unified L3 cache lines per tag |
| 7...0 |
unified L3 cache line size in bytes |
|
| notes |
descriptions |
|
| #1 |
A unified L2 TLB is indicated by a value of 0000h in the upper 16 bits. |
| #2 |
0000b=disabled,
0001b=1-way, 0010b=2-way, 0011b=3-way, 0100b=4-way, 0101b=6-way, 0110b=8-way, 1000b=16-way,
1001b=see leaf 8000_001Dh instead,
1010b=32-way, 1011b=48-way, 1100b=64-way, 1101b=96-way, 1110b=128-way, 1111b=full
|
| #3 |
The AMD K7 processor's L2 cache must be configured prior to relying upon this information, if the model is 1 or 2. |
| #4 |
AMD K7 processors with CPUID=0630h (Duron) inadvertently report 1 KB instead of 64 KB. |
| #5 |
VIA C3 processors with CPUID=0670...068Fh (C5B/C5C) inadvertently use bits 31...24, 23...16, and 15...8 instead. |
| #6 |
VIA C3 processors with CPUID=069x (C5XL) and stepping 1 inadvertently report 0 ways instead of 16 ways. |
extended leaf 8000_0007h
|
|
| input |
EAX=8000_0007h |
get capabilities |
|
| output |
EAX |
processor feedback capabilities |
| bits |
description |
| 31...16 |
maximum wrap time in ms |
| 15...8 |
version (01h) |
| 7...0 |
number of monitors (MSR C001_008[01]h etc.) |
| EBX |
RAS capabilities |
| bits |
description |
| 31...6 |
reserved |
| 5 (LWSMI) |
lightweight SMI (MSR C001_012[3-4]h) |
| 4 (PFEH) |
platform first error handling (MSR C001_012[0-2]h) |
| 3 (SCMCA) |
scalable MCA (more banks, MCA ext regs, DOER/SEER roles) |
| 2 (HWA) |
hardware assert (MSR C001_10[DF...C0]h) |
| 1 (SUCCOR) |
software uncorrectable error containment and recovery |
| 0 (MCAOVR) |
MCA overflow recovery |
| ECX |
advanced power monitoring interface |
| bits |
description |
31...0
(CmpUnitPwrSampleTimeRatio) |
ratio of power accumulator sample period to GTSC counter period |
| EDX |
enhanced power management capabilities |
| bits |
description |
| 31...17 |
reserved |
| 16 (CPPC_PRIO) |
CPPC performance priority |
| 15 (CPPC_FAST) |
CPPC fast |
| 14 (RAPL) |
running average power limit |
| 13 (CSB) |
connected standby |
| 12 (PA) |
processor accumulator (MSR C001_007Ah) |
| 11 (PFI) |
processor feedback interface (see EAX) |
| 10 (EFRO) |
read-only MPERF/APERF (MSR C000_00E[78]h) |
| 9 (CPB) |
core performance boost |
| 8 (ITSC) |
invariant TSC |
| 7 (HWPS) |
hardware P-state support |
| 6 (MUL100) |
100 MHz multiplier steps |
| 5 (STC) |
software thermal control |
| 4 (TM) |
thermal monitoring |
| 3 (TTP) |
thermal trip |
| 2 (VID) |
voltage ID control |
| 1 (FID) |
frequency ID control |
| 0 (TS) |
temperature sensor |
extended leaf 8000_0008h
|
|
| input |
EAX=8000_0008h |
get miscellaneous information |
|
| output |
EAX |
address size information |
| bits |
description |
| 31...24 |
reserved |
| 23...16 |
guest physical address bits (if 0, then see bits 7...0) |
| 15...8 |
virtual address bits |
| 7...0 |
physical address bits |
| EBX |
feature flags |
| bits |
description |
| 31 (BRS) |
Branch Sampling |
| 30 (IBPB_RET) |
PRED_CMD.IBPB clears Return Address Predictor |
| 29 (BTC_NO) |
not affected by Branch Type Confusion |
| 28 (PSFD) |
SPEC_CTRL.PSFD Predictive Store Forward Disable |
| 27 (CPPC) |
Collaborative Processor Performance Control |
| 26 (SSBD_NOT_R.) |
SSBD not required |
| 25 (SSBD_VIRT) |
use VIRT_SPEC_CTL (C001_011Fh) for SSBD |
| 24 (SSBD) |
SPEC_CTRL.SSBD Speculative Store Bypass Disable |
| 23 (PPIN) |
protected processor inventory number, PPIN_CTL and PPIN MSRs |
| 22 (LBR_TSX) |
LBR TSX info |
| 21 (INVLPGB_NP) |
INVLPGB support for invalidating guest nested translations |
| 20 (NO_LMSLE) |
EFER.LMSLE not supported |
| 19 (IBRS_SAME) |
IBRS provides same mode speculation limits |
| 18 (IBRS_PREF) |
IBRS preferred over software solution |
| 17 (STIBP_ALL) |
STIBP always on preferred |
| 16 (IBRS_ALL) |
IBRS always on preferred |
| 15 (STIBP) |
SPEC_CTRL.STIBP |
| 14 (IBRS) |
SPEC_CTRL.IBRS |
| 13 (INT_WBINVD) |
interruptible INVD/WBINVD, EFER.INT_WBINVD_E |
| 12 (IBPB) |
PRED_CMD.IBPB |
| 11 |
unknown – 1 on 4700S (PS5) |
| 10 (LBR_EXT_V1) |
LBR extensions v1 (replaced by v2 in extended leaf 8000_0022h EAX bit 1) |
| 9 (WBNOINVD) |
WBNOINVD |
| 8 (MCOMMIT) |
EFER.MCOMMIT, MCOMMIT |
| 7 |
unknown – 1 on 4700S (PS5) |
| 6 (BE) |
bandwidth enforcement extension |
| 5 |
unknown – 1 on 4700S (PS5) |
| 4 (RDPRU) |
CR4.TSD, RDPRU |
| 3 (INVLPGB) |
INVLPGB and TLBSYNC |
| 2 (ASRFPEP) |
always save/restore FP error pointers |
| 1 (IRPERF) |
read-only IRPERF (MSR C000_00E9h) |
| 0 (CLZERO) |
CLZERO |
| ECX |
processor count information |
| bits |
description |
| 31...18 |
reserved |
| 17...16 |
performance TSC size (00b=40-bit, 01b=48-bit, 10b=56-bit, 11b=64-bit) |
| 15...12 |
number of LSBs in APIC ID that indicate core ID |
| 11...8 |
reserved |
| 7...0 |
cores per die - 1 |
| EDX |
miscellaneous information |
| bits |
description |
| 31...16 |
maximum valid ECX value for RDPRU (0=MPERF, 1=APERF) |
| 15...0 |
INVLPGB maximum page count |
extended leaf 8000_000Ah
|
|
| input |
EAX=8000_000Ah |
get SVM information |
|
| output |
EAX |
revision and presence information |
| bits |
description |
| 31...9 |
reserved |
| 8 |
hypervisor present (and intercepting this bit, to advertise its presence) |
| 7...0 |
revision, starting at 1 |
| EBX |
address space information |
| bits |
description |
| 31...0 |
number of ASIDs |
| ECX |
sub-feature information |
| bits |
description |
| 31...7 |
reserved |
| 6 (x2AVIC_EXT) |
4096 vCPUs supported in x2AVIC mode |
| 5 |
reserved |
| 4 (PML) |
page modification logging (VMCB.90h.11=en, VMCB.1C8h.PML_BASE, VMCB.1D0h.PML_INDEX) |
| 3 (GuestPmcFilt) |
guest PMC event filtering |
| 2...0 |
reserved |
| EDX |
sub-feature information |
| bits |
description |
| 31 (EnhShutIntc) |
enhanced shutdown intercept |
| 30 (IdleHltIntc) |
idle HLT intercept |
| 29 (BusLockThr) |
bus lock threshold |
| 28 (VmcbAddrChk) |
guest VMCB address check |
| 27 (ExtAvAcCh) |
extended interrupt LVT register AVIC access changes
0 = read –> #VMEXIT(fault)
write –> #VMEXIT(fault)
1 = read –> allowed
write –> #VMEXIT(trap)
|
| 26 (IbsVirt) |
IBS virtualization |
| 25 (VNMI) |
NMI virtualization |
| 24 (TlbiCtl) |
INVLPGB/TLBSYNC HV enable in VMCB and TLBSYNC intercept |
| 23 (HOST_MCE) |
if hCR4.MCE=1 gCR4.MCE=0, #MC in guest = intercept not shutdown |
| 22 |
reserved |
| 21 (ROGPT) |
read-only guest page table feature support |
| 20 (SPEC_CTRL) |
SPEC_CTRL virtualization |
| 19 (SSS_CHECK) |
SVM supervisor shadow stack restrictions |
| 18 (x2AVIC) |
AVIC for x2APIC mode |
| 17 (GMET) |
guest mode execution trap |
| 16 (VGIF) |
virtualized GIF |
| 15 (VLS) |
virtualized VMLOAD/VMSAVE |
| 14 |
reserved |
| 13 (AVIC) |
AVIC |
| 12 (PAUSEFILTERTHR.) |
PAUSE filter threshold |
| 11 (EMP) |
encrypted microcode patch |
| 10 (PAUSEFILTER) |
PAUSE intercept filter |
| 9 (SSSE3SSE5ADIS) |
SSSE3 and SSE5A disable |
| 8 (PmcVirt) |
PMC virtualization |
| 7 (DECODEASSISTS) |
decode assists |
| 6 (FLUSHBYASID) |
flush by ASID |
| 5 (VMCBCLEAN) |
VMCB clean bits |
| 4 (TSCRATEMSR) |
MSR-based TSC rate control |
| 3 (NRIPS) |
NRIP save on #VMEXIT |
| 2 (SVML) |
SVM lock |
| 1 (LBRV) |
LBR virtualization |
| 0 (NP) |
nested paging |
extended leaf 8000_0019h
|
|
| input |
EAX=8000_0019h |
get TLB configuration descriptors |
|
| output |
EAX |
1 GB L1 TLB configuration descriptor #1 |
| bits |
description |
| 31...28 |
data TLB associativity #2 |
| 27...16 |
data TLB entries |
| 15...12 |
code TLB associativity #2 |
| 11...0 |
code TLB entries |
| EBX |
1 GB L2 TLB configuration descriptor #1 |
| bits |
description |
| 31...28 |
data TLB associativity #2 |
| 27...16 |
data TLB entries |
| 15...12 |
code TLB associativity #2 |
| 11...0 |
code TLB entries |
|
| notes |
descriptions |
|
| #1 |
A unified TLB is indicated by a value of 0000h in the upper 16 bits. |
| #2 |
0000b=disabled, 0001b=1-way, 0010b=2-way, 0100b=4-way, 0110b=8-way, 1000b=16-way,
1010b=32-way, 1011b=48-way, 1100b=64-way, 1101b=96-way, 1110b=128-way, 1111b=full
|
extended leaf 8000_001Ah
|
|
| input |
EAX=8000_001Ah |
get performance optimization identifiers |
|
| output |
EAX |
performance optimization identifiers |
| bits |
description |
| 31...4 |
reserved |
| 3 (FP512) |
1x 512-bit instead of 2x 256-bit processing |
| 2 (FP256) |
1x 256-bit instead of 2x 128-bit processing |
| 1 (MOVU) |
prefer unaligned MOV over MOVL/MOVH |
| 0 (FP128) |
1x 128-bit instead of 2x 64-bit processing |
extended leaf 8000_001Bh
|
|
| input |
EAX=8000_001Bh |
get IBS information |
|
| output |
EAX |
IBS feature flags |
| bits |
description |
| 31...20 |
reserved |
| 19 |
simplified DTLB page size and miss reporting in IBS_OP_DATA3 |
| 18 |
IBS memory profiler v1 |
| 17 |
IBS buffer v1 |
| 16 |
IBS filtering for streaming stores and remote socket |
| 15 |
IBS filtering for instruction address bit 63 being 0/1 |
| 14 |
IBS filtering for fetch latency |
| 13 |
IBS alternate fetch and execution disable bits |
| 12 |
IBS filtering by load latency |
| 11 |
IBS filtering for L3 miss |
| 10 |
IBS op data 4 MSR |
| 9 |
IBS fetch control extended MSR |
| 8 |
fused branch micro-op indication |
| 7 |
invalid RIP indication |
| 6 |
IbsOpCurCnt and IbsOpMaxCnt extend by 7 bits |
| 5 |
branch target address reporting |
| 4 |
op counting mode |
| 3 |
read write of op counter |
| 2 |
IBS execution sampling |
| 1 |
IBS fetch sampling |
| 0 |
IBS feature flags valid |
extended leaf 8000_001Ch
|
|
| input |
EAX=8000_001Ch |
get LWP information |
|
| output |
EAX |
bits |
description |
| 31 |
interrupt on threshold overflow available |
| 30 |
performance time stamp counter in event record available |
| 29 |
sampling in continuous mode available |
| 28...7 |
reserved |
| 6 |
core reference clocks not halted event available |
| 5 |
core clocks not halted event available |
| 4 |
DC miss event available |
| 3 |
branch retired event available |
| 2 |
instructions retired event available |
| 1 |
LWPVAL instruction available |
| 0 |
LWP available (copy of XCR0.LWP) |
| EBX |
bits |
description |
| 31...24 |
EventInterval1 field offset |
| 23...16 |
maximum EventId |
| 15...8 |
event record size |
| 7...0 |
control block size |
| ECX |
bits |
description |
| 31 |
cache latency filtering supported |
| 30 |
cache level filtering supported |
| 29 |
IP filtering supported |
| 28 |
branch prediction filtering supported |
| 27...24 |
reserved |
| 23...16 |
event ring buffer size |
| 15...9 |
version |
| 8...6 |
amount by which cache latency is rounded |
| 5 |
data cache miss address valid |
| 4...0 |
latency counter bit size |
| EDX |
bits |
description |
| 31 |
interrupt on threshold overflow supported |
| 30 |
performance time stamp counter in event record supported |
| 29 |
sampling in continuous mode supported |
| 28...7 |
reserved |
| 6 |
core reference clocks not halted event supported |
| 5 |
core clocks not halted event supported |
| 4 |
DC miss event supported |
| 3 |
branch retired event supported |
| 2 |
instructions retired event supported |
| 1 |
LWPVAL instruction supported |
| 0 |
LWP supported (copy of LWP feature flag in extended leaf 8000_0001h) |
extended leaf 8000_001Dh
|
|
| input |
EAX=8000_001Dh |
get cache configuration descriptors |
| ECX=xxxx_xxxxh |
cache level to query (until EAX reports cache type = 0) |
|
| output |
EAX |
bits |
description |
| 31...26 |
reserved |
| 25...14 |
cores per cache - 1 |
| 13...10 |
reserved |
| 9 |
fully associative? |
| 8 |
self-initializing? |
| 7...5 |
cache level (starts at 1) |
| 4...0 |
cache type (0=null, 1=data, 2=code, 3=unified, 4...31=reserved) |
| EBX |
bits |
description |
| 31...22 |
ways of associativity - 1 |
| 21...12 |
physical line partitions - 1 |
| 11...0 |
system coherency line size - 1 |
| ECX |
bits |
description |
| 31...0 |
sets - 1 |
| EDX |
bits |
description |
| 31...2 |
reserved |
| 1 |
inclusive of lower levels? |
| 0 |
write-back invalidate? |
extended leaf 8000_001Eh
|
|
| input |
EAX=8000_001Eh |
get APIC/unit/node information |
|
| output |
EAX |
extended APIC ID |
| bits |
description |
| 31...0 |
extended APIC ID |
| EBX |
compute unit identifiers (Fam 15h)
core identifiers (Fam 17h)
|
| bits |
description |
| 31...16 |
reserved |
| 15...8 |
cores per compute unit - 1 (Fam 15h)
threads per core - 1 (Fam 17h)
|
| 7...0 |
compute unit ID (Fam 15h)
core ID (Fam 17h)
|
| ECX |
node identifiers |
| bits |
description |
| 31...11 |
reserved |
| 10...8 |
nodes per processor - 1 |
| 7...0 |
node ID |
extended leaf 8000_001Fh
|
|
| input |
EAX=8000_001Fh |
get SME/SEV information |
|
| output |
EAX |
bits |
description |
| 31 |
IBPB on entry |
| 30 |
AMD: writes to HV-owned pages are allowed when marked in-use
Hygon CSV3 (C001_0131h.CSV3[30])
(i.e. AMD and Hygon differ for this bit – see e.g. here and here, as well as here and here for more details) |
| 29 |
VIRT_RMPUPDATE and VIRT_PSMASH MSR (C001_F00[12]h) |
| 28 |
SVSM communication page MSR (C001_F000h) |
| 27 |
allowed SEV features |
| 26 |
secure AVIC |
| 25 |
SMT protection |
| 24 |
VMSA register protection |
| 23 |
segmented RMP |
| 22 |
guest intercept control |
| 21 |
RMPREAD |
| 20 |
PMC virtualization for SEV-ES and SEV-SNP guests |
| 19 |
IBS virtualization for SEV-ES and SEV-SNP guests |
| 18 |
virtual TOM MSR |
| 17 |
VMGEXIT parameter |
| 16 |
VTE virtual transparent encryption |
| 15 |
disallowing IBS use by the host |
| 14 |
debug state virtualization for SEV-ES and SEV-NP guests |
| 13 |
alternate injection |
| 12 |
restricted injection |
| 11 |
SEV guest execution only allowed from a 64-bit host |
| 10 |
hardware cache coherency across encryption domains enforced |
| 9 |
TSC AUX virtualization |
| 8 |
secure TSC |
| 7 |
VMPL supervisor shadow stack |
| 6 |
RMPQUERY |
| 5 |
VM permission levels |
| 4 |
SEV-SNP |
| 3 |
SEV-ES, VMGEXIT, #VC, GHCB MSR (C001_0130h)
Hygon CSV2 (C001_0131h.CSV2[1]) |
| 2 |
VMPAGE_FLUSH MSR (C001_011Eh) |
| 1 |
SEV
Hygon CSV1 (C001_0131h.CSV1[0]) |
| 0 |
SME |
| EBX |
bits |
description |
| 31...16 |
reserved |
| 15...12 |
number of supported VM permission levels |
| 11...6 |
hPA bit count reduction when memory encryption is active |
| 5...0 |
page table bit position used to indicate memory encryption |
| ECX |
bits |
description |
| 31...0 |
number of simultaneously supported encrypted guests |
| EDX |
bits |
description |
| 31...0 |
minimum SEV enabled, SEV-ES disabled ASID |
standard leaf 8000_0020h
|
|
| input |
EAX=8000_0020h |
get platform QoS enumeration |
| ECX=0000_00xxh |
sub-leaf to query (0=resources, 1...n as per EBX reported by sub-leaf 0) |
|
output
(sub 0)
(main) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31...10 |
reserved |
| 9 (PLZA) |
privilege level zero association – PQR_PLZA_ASSOC MSR (C000_03FCh) |
| 8 (GLSBE) |
global slow bandwidth enforcement |
| 7 (GLBE) |
global bandwidth enforcement |
| 6 (SDCIAE) |
SDCI allocation enforcement |
| 5 (ABMC) |
assignable bandwidth monitoring counters |
| 4 (L3RR) |
L3 range reservations |
| 3 (BMEC) |
bandwidth monitoring event configuration |
| 2 (L3SBME) |
slow memory bandwidth enforcement |
| 1 (L3BME) |
memory bandwidth enforcement |
| 0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(sub 1)
(L3MBE) |
EAX |
bits |
description |
| 31...0 (BW_LEN) |
size of bandwidth specifier field in L3QOS_BW_CONTROL_n MSRs |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 (COS_MAX) |
maximum COS number for L3MBE |
|
output
(sub 2)
(L3SMBE) |
EAX |
bits |
description |
| 31...0 (BW_LEN) |
size of bandwidth specifier field in L3QOS_SLOWBW_CONTROL_n MSRs |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 (COS_MAX) |
maximum COS number for L3SMBE |
|
output
(sub 3)
(BMEC) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31...8 |
reserved |
| 7...0 (EVT_NUM) |
number of configurable bandwidth events |
| ECX |
bits |
description |
| 31...7 |
reserved |
| 6 |
dirty victim writes |
| 5 |
remote slow reads |
| 4 |
local slow reads |
| 3 |
remote NT writes |
| 2 |
local NT writes |
| 1 |
remote reads |
| 0 |
local reads |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(sub 4)
(L3RR) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(sub 5)
(ABMC) |
EAX |
bits |
description |
| 31...9 |
reserved |
| 8 |
counter bit 61 is overflow bit |
| 7...0 |
counter width, offset from 24 bits (if 0, use FMS to pick the width) |
| EBX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
maximum supported ABMC counter ID |
| ECX |
bits |
description |
| 31...1 |
reserved |
| 0 |
counters can be configured to count by COS instead of RMID |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(sub 6)
(SDCIAE) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
|
output
(sub 7)
(GLBE) |
EAX |
bits |
description |
| 31...0 (BW_LEN) |
size of ceiling field in L3QOS_GL_BW_CONTROL_n MSRs |
| EBX |
bits |
description |
| 31...16 |
reserved |
| 15...0 (BW_MULT) |
units of GLBE bandwidth ceiling as configured by the ceiling field
of L3QOS_GL_BW_CONTROL_n MSRs (C000_0600h+)
units = 1/8 GB/s * (BW_MULT+1)
|
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 (COS_MAX) |
maximum COS number for GLBE |
|
output
(sub 8)
(GLSBE) |
EAX |
bits |
description |
| 31...0 (BW_LEN) |
size of ceiling field in L3QOS_GL_SLOWBW_CONTROL_n MSRs |
| EBX |
bits |
description |
| 31...16 |
reserved |
| 15...0 (BW_MULT) |
units of GLSBE bandwidth ceiling as configured by the ceiling field
of L3QOS_GL_SLOWBW_CONTROL_n MSRs (C000_0680h+)
units = 1/8 GB/s * (BW_MULT+1)
|
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 (COS_MAX) |
maximum COS number for GLSBE |
|
output
(sub 9)
(PLZA) |
EAX |
bits |
description |
| 31...0 |
reserved |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
extended leaf 8000_0021h
|
|
| input |
EAX=8000_0021h |
get feature information |
|
| output |
EAX |
bits |
description |
| 31 |
SRSO_MSR_FIX – MSR_BP_CFG[BpSpecReduce] = SRSO mitigation |
| 30 |
SRSO_USER_KERNEL_NO |
| 29 |
SRSO_NO |
| 28 |
PRED_CMD.IBPB clears all branch type predictions |
| 27 |
PRED_CMD.SBPB |
| 26 |
UAIv2, EFER.UAI_[S,U]_E, CR3.LAM_U_57 |
| 25 |
reserved |
| 24 |
ERAPS |
| 23 |
AVX512BMM – VBMAC[OR,XOR]16X16X16, VBITREVB |
| 22 |
workload class, extended leaf 8000_0027h |
| 21 |
FP512 downgraded to FP256, via HWCR[34]=1 |
| 20 |
PREFETCHIT0/PREFETCHIT1 |
| 19 |
fast short REP SCASB |
| 18 |
EPSF – enhanced PSF (see AMD PSF WP for details) |
| 17 |
CPUID at CPL>0 outside SMM may #GP – HWCR[35] = enable bit |
| 16 |
0Fh,01h,/7 opcode space is reserved for AMD use |
| 15 |
enhanced REP MOVSB/STOSB |
| 14 |
L2 TLB sizes are encoded as multiples of 32 |
| 13 |
PREFETCH_CTRL MSR |
| 12 |
PerfEvtSel2[PreciseRetire] |
| 11 |
fast short REPE CMPSB |
| 10 |
fast short REP STOSB |
| 9 |
SMM_CTL MSR (C001_0116h) not supported |
| 8 |
automatic IBRS |
| 7 |
UAIv1, EFER.UAI_V1_E |
| 6 |
null sreg.sel load also clears sreg.bas and sreg.lim |
| 5 |
VERW for TSA mitigation (bit won't be set after microcode loaded – instead HV must synthesize it) |
| 4 |
TSX_CTRL |
| 3 |
SMM paging configuration lock |
| 2 |
LFENCE always dispatch serializing |
| 1 |
FS_BAS, GS_BAS, and KERNEL_GS_BAS writes are non-serializing |
| 0 |
processor ignores nested data breakpoints |
| EBX |
bits |
description |
| 31...24 |
reserved |
| 23...16 |
RAP size (Zen5: 64, if 0: assume 32) |
| 15...0 |
microcode patch block (MPB) size in 16-byte multiples (if 0: assume 5568 bytes) |
| ECX |
bits |
description |
| 31...3 |
reserved |
| 2 |
TSA_L1_NO (TSA affects Zen3/Zen4, but not pre-Zen3 or Zen5 – if unaffected, HV could synthesize it) |
| 1 |
TSA_SQ_NO (TSA affects Zen3/Zen4, but not pre-Zen3 or Zen5 – if unaffected, HV could synthesize it) |
| 0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
extended leaf 8000_0022h
|
|
| input |
EAX=8000_0022h |
get extended performance monitoring and debug information |
|
| output |
EAX |
bits |
description |
| 31...3 |
reserved |
| 2 |
can freeze core perf counters and LBR stack on perf counter overflow |
| 1 |
LBR extensions v2 – stack |
| 0 |
PerfMonV2 |
| EBX |
bits |
description |
| 31...27 |
reserved |
| 26...24 |
UMC channel group ID (for MIxxx) |
| 23...16 |
number of UMC performance counters |
| 15...10 |
number of NB performance counters |
| 9...4 |
number of LBR stack entries |
| 3...0 |
number of core performance counters |
| ECX |
bits |
description |
| 31...0 |
bitmask for active UMCs |
| EDX |
bits |
description |
| 31...0 |
reserved |
extended leaf 8000_0023h
|
|
| input |
EAX=8000_0023h |
get secure host multi-key memory encryption information |
|
| output |
EAX |
bits |
description |
| 31...1 |
reserved |
| 0 |
secure HMK-MEM encryption mode supported |
| EBX |
bits |
description |
| 31...16 |
reserved |
| 15...0 |
number of simultaneously available host encryption key IDs |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
extended leaf 8000_0025h
|
|
| input |
EAX=8000_0025h |
get RMP information |
|
| output |
EAX |
bits |
description |
| 31...12 |
reserved |
| 11...6 |
maximum supported RMP segment size |
| 5...0 |
minimum supported RMP segment size |
| EBX |
bits |
description |
| 31...11 |
reserved |
| 10 |
number of RMP segments is reduced |
| 9...0 |
number of cached RMP segment definitions |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...3 |
reserved |
| 2 |
RMPCHKD and RMP Dirty |
| 1 |
enhanced SMT protection |
| 0 |
RMPOPT |
standard leaf 0000_0026h
|
|
| input |
EAX=0000_0026h |
get topology enumeration information |
| ECX=xxxx_xxxxh |
sub-leaf to query (0...n until ECX[15...8] = 0) |
|
output
(sub n) |
EAX |
bits |
description |
| 31 |
supports asymmetric |
| 30 |
supports heterogeneous |
| 29 |
supports power efficiency ranking (for type=core) |
| 28...5 |
reserved |
| 4...0 |
number of bits that x2APIC ID must be shifted to right for next domain |
| EBX |
bits |
description |
| 31...28 |
core type value (for type=core) |
| 27...24 |
native model ID (for type=core) |
| 23...16 |
power efficiency ranking (for type=core) |
| 15...0 |
number of logical processors across all the instances of this domain |
| ECX |
bits |
description |
| 31...16 |
reserved |
| 15...8 |
domain type
(0=reserved, 1=core, 2=complex, 3=die, 4=socket, 5-255=reserved) |
| 7...0 |
input ECX sub-leaf index |
| EDX |
bits |
description |
| 31...0 |
x2APIC ID – always valid – does not vary with sub-leaf index |
extended leaf 8000_0027h
|
|
| input |
EAX=8000_0027h |
get workload class information |
|
| output |
EAX |
bits |
description |
| 31...4 |
reserved |
| 3...0 |
number of workload class IDs |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...0 |
reserved |
Transmeta leaf 8086_0000h
|
|
| input |
EAX=8086_0000h |
get maximum supported leaf and vendor ID string |
|
| output |
EAX=xxxx_xxxxh |
maximum supported leaf |
| EBX-EDX-ECX |
vendor ID string |
| TransmetaCPU |
Transmeta processor |
Transmeta leaf 8086_0001h
|
|
| input |
EAX=8086_0001h |
get processor information |
|
| output |
EAX=xxxx_xxxxh |
processor family/model/stepping |
extended family
(add)
|
The extended processor family is encoded in bits 27...20. |
|
00+0 |
Transmeta Efficeon |
extended model
(concat)
|
The extended processor model is encoded in bits 19...16. |
| Transmeta Crusoe |
0 |
TM3x00 and TM5x00 |
| Transmeta Efficeon |
0 |
TM8000 |
| family |
The family is encoded in bits 11...8. |
|
5 |
Transmeta Crusoe |
| F |
refer to extended family |
| model |
The model is encoded in bits 7...4. |
| Transmeta Crusoe |
4 |
TM3x00 and TM5x00 |
| Transmeta Efficeon |
2 |
TM8000 (130 nm) |
| 2 |
TM8000 (90 nm CMS 6.0) |
| 3 |
TM8000 (90 nm CMS 6.1+) |
| stepping |
The stepping is encoded in bits 3...0. |
| The stepping values are processor-specific. |
| EBX=aabb_ccddh |
hardware revision (a.b-c.d)
0101_xxyyh = TM3200
0102_xxyyh = TM5400
0103_xxyyh = TM5400 or TM5600
0103_00yyh = TM5500 or TM5800
0104_xxyyh = TM5500 or TM5800
0105_xxyyh = TM5500 or TM5800
0200_0000h = see leaf 8086_0002h register EAX
|
| ECX=xxxx_xxxxh |
nominal core clock frequency (MHz) |
| EDX=xxxx_xxxxh |
feature flags |
description of indicated feature |
| 31...4 |
reserved |
| 3 (LRTI) |
LongRun Table Interface |
| 2 (???) |
unknown |
| 1 (LR) |
LongRun |
| 0 (BAD) |
recovery CMS active (due to a failed upgrade) |
Transmeta leaf 8086_0002h
|
|
| input |
EAX=8086_0002h |
get processor information |
|
| output |
EAX |
xxxx_xxxxh |
reserved or hardware revision (xxxxxxxxh)
see leaf 8086_0001h register EBX
|
| EBX |
aabb_ccddh |
software revision, part 1/2 (a.b.c-d-x) |
| ECX |
xxxx_xxxxh |
software revision, part 2/2 (a.b.c-d-x) |
Transmeta leaves 8086_0003h, 8086_0004h, 8086_0005h, and 8086_0006h
|
|
| input |
EAX=8086_0003h |
get information string (part 1) |
| EAX=8086_0004h |
get information string (part 2) |
| EAX=8086_0005h |
get information string (part 3) |
| EAX=8086_0006h |
get information string (part 4) |
|
| output |
EAX-EBX-ECX-EDX
|
information string #1 |
| Transmeta |
20000805 23:30 official release 4.1.4#2 (example) |
|
| note |
description |
|
| #1 |
Unused characters at the end of the string are filled with 00h. |
Transmeta leaf 8086_0007h
|
|
| input |
EAX=8086_0007h |
get processor information |
|
| output |
EAX |
xxxx_xxxxh |
current core clock frequency (MHz) |
| EBX |
xxxx_xxxxh |
current core clock voltage (mV) |
| ECX |
xxxx_xxxxh |
current (LongRun) performance level (0...100%) |
| EDX |
xxxx_xxxxh |
current gate delay (fs) |
Hygon leaf 8C86_0000h
|
|
| input |
EAX=8C86_0000h |
get maximum supported leaf and feature flags |
|
| output |
EAX |
bits |
description |
| 31...0 |
maximum supported leaf |
| EBX |
bits |
description |
| 31...0 |
reserved |
| ECX |
bits |
description |
| 31...0 |
reserved |
| EDX |
bits |
description |
| 31...3 |
reserved |
| 2 |
SM4 |
| 1 |
SM3 |
| 0 |
reserved |
Centaur and Zhaoxin leaf C000_0000h
|
|
| input |
EAX=C000_0000h |
get maximum supported leaf |
|
| output |
EAX=xxxx_xxxxh |
maximum supported leaf |
Centaur and Zhaoxin leaf C000_0001h
|
|
| input |
EAX=C000_0001h |
get processor information |
|
| output |
EDX=xxxx_xxxxh
(Centaur) |
feature flags |
description of indicated feature |
| 31...14 |
reserved |
| 13 (PMM-E) |
PadLock Montgomery Multiplier enabled |
| 12 (PMM-P) |
PadLock Montgomery Multiplier present |
| 11 (PHE-E) |
PadLock Hash Engine enabled |
| 10 (PHE-P) |
PadLock Hash Engine present |
| 9 (A`2/MM/HE-E) |
ACE2 and Montgomery Multiplier and Hash Engine enabled |
| 8 (A`2/MM/HE-P) |
ACE2 and Montgomery Multiplier and Hash Engine present |
| 7 (ACE-E) |
Advanced Cryptography Engine enabled |
| 6 (ACE-P) |
Advanced Cryptography Engine present |
| 5 (FEMMS) |
FEMMS |
| 4 (LH) |
LongHaul MSR 0000_110Ah |
| 3 (RNG-E) |
Random Number Generator enabled |
| 2 (RNG-P) |
Random Number Generator present |
| 1 (AIS-E) |
Alternate Instruction Set enabled |
| 0 (AIS-P) |
Alternate Instruction Set present |
|
| output |
EDX=xxxx_xxxxh
(Zhaoxin) |
feature flags |
description of indicated feature |
| 31 (STK) |
STK |
| 30 (VEX-E) |
VEX Instructions enabled |
| 29 (VEX-P) |
VEX Instructions present |
| 28 (RSA-E) |
RSA (XMODEXP/MONTMUL2) enabled |
| 27 (RSA-P) |
RSA (XMODEXP/MONTMUL2 present) |
| 26 (PHE2-E) |
PadLock Hash Engine 2 (SHA384/SHA512) enabled |
| 25 (PHE2-P) |
PadLock Hash Engine 2 (SHA384/SHA512) present |
| 24 (SME) |
SME |
| 23 (RNG2-E) |
Random Number Generator 2 enabled |
| 22 (RNG2-P) |
Random Number Generator 2 present |
| 21 (TM3-E) |
Thermal Monitor 3 enabled |
| 20 (TM3-P) |
Thermal Monitor 3 present |
| 19 (O`STRESS-E) |
Overstress Feature for Auto Overclock enabled |
| 18 (O`STRESS-P) |
Overstress Feature for Auto Overclock present |
| 17 (PARALLAX-E) |
Adaptive P-State Control enabled |
| 16 (PARALLAX-P) |
Adaptive P-State Control present |
| 15 (FMA) |
FMA |
| 14 |
reserved |
| 13 (PMM-E) |
PadLock Montgomery Multiplier enabled |
| 12 (PMM-P) |
PadLock Montgomery Multiplier present |
| 11 (PHE-E) |
PadLock Hash Engine enabled |
| 10 (PHE-P) |
PadLock Hash Engine present |
| 9 (A`2/MM/HE-E) |
ACE2 and Montgomery Multiplier and Hash Engine enabled |
| 8 (A`2/MM/HE-P) |
ACE2 and Montgomery Multiplier and Hash Engine present |
| 7 (ACE-E) |
Advanced Cryptography Engine enabled |
| 6 (ACE-P) |
Advanced Cryptography Engine present |
| 5 (SM3/SM4-E) |
SM3 and SM4 enabled [was FEMMS for Centaur] |
| 4 (SM3/SM4-P) |
SM3 and SM4 present [was LH MSR for Centaur] |
| 3 (RNG-E) |
Random Number Generator enabled |
| 2 (RNG-P) |
Random Number Generator present |
| 1 (SM2-E) |
SM2 enabled [was AIS enabled for Centaur] |
| 0 (SM2-P) |
SM2 present [was AIS present for Centaur] |
Zhaoxin leaf C000_0002h
|
|
| input |
EAX=C000_0002h |
unknown |
|
| output |
EAX-EBX-ECX-EDX |
bits |
description |
| 31...0 |
unknown |
Zhaoxin leaf C000_0003h
|
|
| input |
EAX=C000_0003h |
unknown |
|
| output |
EAX-EBX-ECX-EDX |
bits |
description |
| 31...0 |
unknown |
Zhaoxin leaf C000_0004h
|
|
| input |
EAX=C000_0004h |
unknown |
|
| output |
EAX-EBX-ECX-EDX |
bits |
description |
| 31...0 |
unknown |
Zhaoxin leaf C000_0005h
|
|
| input |
EAX=C000_0005h |
get isolation information |
|
| output |
EAX |
bits |
description |
| 31...0 |
reserved |
| 7 |
isolated memory supported (think "PRMRR support") |
| 6...0 |
isolated memory region count (think "PRMRR count") |
Zhaoxin leaf C000_0006h
|
|
| input |
EAX=C000_0006h |
get processor information |
|
| output |
EAX=xxxx_xxxxh |
feature flags |
description of indicated feature |
| 31...1 |
reserved |
| 0 (PAUSEOPT) |
PAUSEOPT |
AMD prank leaf 8FFF_FFFEh
|
|
| input |
EAX=8FFF_FFFEh |
end of range – 1 #1 |
|
| output |
EAX |
0049_4544h |
DEI |
| EBX |
0000_0000h |
reserved |
| ECX |
0000_0000h |
reserved |
| EDX |
0000_0000h |
reserved |
|
| note |
description |
|
| #1 |
This leaf is only supported by the AMD K6 processor family. |
AMD prank leaf 8FFF_FFFFh
|
|
| input |
EAX=8FFF_FFFFh |
end of range #1 |
|
| output |
EAX
EBX
ECX
EDX
|
string |
NexGenerationAMD (K6)
IT'S HAMMER TIME (K8)
HELLO KITTY! ^-^ (KB,ML)
|
|
| note |
description |
|
| #1 |
This leaf is only supported by the indicated processor families. |
Rise mP6 prank leaf 0000_5A4Eh
|
|
| input |
EAX=0000_5A4Eh |
ASCII of New Zealand #1 |
|
| output |
EBX-EDX-ECX-EAX |
string |
* Chris Norrie * |
|
| note |
description |
|
| #1 |
This leaf is only supported by the Rise mP6 processor. |
reserved leaf
|
|
| input |
EAX=xxxx_xxxxh |
desired CPUID leaf |
|
| output |
EAX=xxxx_xxxxh
EBX=xxxx_xxxxh
ECX=xxxx_xxxxh
EDX=xxxx_xxxxh
|
undefined
The processor may leave the registers unchanged. This is considered legacy behavior as it does add extra software complexity.
The processor may set the registers to the same values as the maximum standard leaf. This is considered deprecated behavior.
The processor may set the registers to zero. This is considered proper behavior.
For reserved CPUID leaves Intel processors with microcode update support and MSRs may or may not write MSR 0000_008Bh. (Do use leaf 1 for it.)
|
© 1996-2026 by Christian Ludloff. All rights reserved. Use at your own risk.
|